drivers/net/ethernet/intel/igb/igb.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/intel/igb/igb.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/intel/igb/igb.h- Extension
.h- Size
- 24612 bytes
- Lines
- 873
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
e1000_mac.he1000_82575.hlinux/timecounter.hlinux/net_tstamp.hlinux/ptp_clock_kernel.hlinux/bitops.hlinux/if_vlan.hlinux/i2c.hlinux/i2c-algo-bit.hlinux/pci.hlinux/mdio.hlinux/lockdep.hnet/xdp.hnet/xdp_sock_drv.h
Detected Declarations
struct igb_adapterstruct vf_data_storagestruct vf_mac_filterstruct igb_tx_bufferstruct igb_rx_bufferstruct igb_tx_queue_statsstruct igb_rx_queue_statsstruct igb_ring_containerstruct igb_ringstruct igb_q_vectorstruct hwmon_attrstruct hwmon_buffstruct igb_nfc_inputstruct igb_nfc_filterstruct igb_mac_addrstruct igb_adapterenum igb_tx_flagsenum igb_tx_buf_typeenum e1000_ring_flags_tenum igb_filter_match_flagsenum e1000_state_tenum igb_boardsfunction igb_compute_padfunction igb_skb_padfunction igb_rx_bufszfunction igb_rx_pg_orderfunction igb_test_staterrfunction igb_desc_unusedfunction igb_reset_phyfunction igb_read_phy_regfunction igb_write_phy_regfunction igb_get_phy_infofunction igb_xdp_ring_update_tailfunction igb_xdp_is_enabled
Annotated Snippet
struct vf_data_storage {
unsigned char vf_mac_addresses[ETH_ALEN];
u16 vf_mc_hashes[IGB_MAX_VF_MC_ENTRIES];
u16 num_vf_mc_hashes;
u32 flags;
unsigned long last_nack;
u16 pf_vlan; /* When set, guest VLAN config not allowed. */
u16 pf_qos;
u16 tx_rate;
bool spoofchk_enabled;
bool trusted;
};
/* Number of unicast MAC filters reserved for the PF in the RAR registers */
#define IGB_PF_MAC_FILTERS_RESERVED 3
struct vf_mac_filter {
struct list_head l;
int vf;
bool free;
u8 vf_mac[ETH_ALEN];
};
#define IGB_VF_FLAG_CTS 0x00000001 /* VF is clear to send data */
#define IGB_VF_FLAG_UNI_PROMISC 0x00000002 /* VF has unicast promisc */
#define IGB_VF_FLAG_MULTI_PROMISC 0x00000004 /* VF has multicast promisc */
#define IGB_VF_FLAG_PF_SET_MAC 0x00000008 /* PF has set MAC address */
/* RX descriptor control thresholds.
* PTHRESH - MAC will consider prefetch if it has fewer than this number of
* descriptors available in its onboard memory.
* Setting this to 0 disables RX descriptor prefetch.
* HTHRESH - MAC will only prefetch if there are at least this many descriptors
* available in host memory.
* If PTHRESH is 0, this should also be 0.
* WTHRESH - RX descriptor writeback threshold - MAC will delay writing back
* descriptors until either it has this many to write back, or the
* ITR timer expires.
*/
#define IGB_RX_PTHRESH ((hw->mac.type == e1000_i354) ? 12 : 8)
#define IGB_RX_HTHRESH 8
#define IGB_TX_PTHRESH ((hw->mac.type == e1000_i354) ? 20 : 8)
#define IGB_TX_HTHRESH 1
#define IGB_RX_WTHRESH ((hw->mac.type == e1000_82576 && \
(adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 4)
#define IGB_TX_WTHRESH ((hw->mac.type == e1000_82576 && \
(adapter->flags & IGB_FLAG_HAS_MSIX)) ? 1 : 16)
/* this is the size past which hardware will drop packets when setting LPE=0 */
#define MAXIMUM_ETHERNET_VLAN_SIZE 1522
#define IGB_ETH_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN + (VLAN_HLEN * 2))
/* Supported Rx Buffer Sizes */
#define IGB_RXBUFFER_256 256
#define IGB_RXBUFFER_1536 1536
#define IGB_RXBUFFER_2048 2048
#define IGB_RXBUFFER_3072 3072
#define IGB_RX_HDR_LEN IGB_RXBUFFER_256
#define IGB_TS_HDR_LEN 16
/* Attempt to maximize the headroom available for incoming frames. We
* use a 2K buffer for receives and need 1536/1534 to store the data for
* the frame. This leaves us with 512 bytes of room. From that we need
* to deduct the space needed for the shared info and the padding needed
* to IP align the frame.
*
* Note: For cache line sizes 256 or larger this value is going to end
* up negative. In these cases we should fall back to the 3K
* buffers.
*/
#if (PAGE_SIZE < 8192)
#define IGB_MAX_FRAME_BUILD_SKB (IGB_RXBUFFER_1536 - NET_IP_ALIGN)
#define IGB_2K_TOO_SMALL_WITH_PADDING \
((NET_SKB_PAD + IGB_TS_HDR_LEN + IGB_RXBUFFER_1536) > SKB_WITH_OVERHEAD(IGB_RXBUFFER_2048))
static inline int igb_compute_pad(int rx_buf_len)
{
int page_size, pad_size;
page_size = ALIGN(rx_buf_len, PAGE_SIZE / 2);
pad_size = SKB_WITH_OVERHEAD(page_size) - rx_buf_len;
return pad_size;
}
static inline int igb_skb_pad(void)
{
int rx_buf_len;
Annotation
- Immediate include surface: `e1000_mac.h`, `e1000_82575.h`, `linux/timecounter.h`, `linux/net_tstamp.h`, `linux/ptp_clock_kernel.h`, `linux/bitops.h`, `linux/if_vlan.h`, `linux/i2c.h`.
- Detected declarations: `struct igb_adapter`, `struct vf_data_storage`, `struct vf_mac_filter`, `struct igb_tx_buffer`, `struct igb_rx_buffer`, `struct igb_tx_queue_stats`, `struct igb_rx_queue_stats`, `struct igb_ring_container`, `struct igb_ring`, `struct igb_q_vector`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.