drivers/net/ethernet/intel/ixgbe/devlink/devlink.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/intel/ixgbe/devlink/devlink.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/intel/ixgbe/devlink/devlink.h- Extension
.h- Size
- 431 bytes
- Lines
- 13
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
- No top-level syscall, struct, function, initcall, or export declaration detected by the generator.
Annotated Snippet
#ifndef _IXGBE_DEVLINK_H_
#define _IXGBE_DEVLINK_H_
struct ixgbe_adapter *ixgbe_allocate_devlink(struct device *dev);
int ixgbe_devlink_register_port(struct ixgbe_adapter *adapter);
void ixgbe_devlink_init_regions(struct ixgbe_adapter *adapter);
void ixgbe_devlink_destroy_regions(struct ixgbe_adapter *adapter);
#endif /* _IXGBE_DEVLINK_H_ */
Annotation
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.