drivers/net/ethernet/jme.h

File Facts

System

Linux kernel

Corpus path

drivers/net/ethernet/jme.h

Extension

.h

Size

30678 bytes

Lines

1264

Domain

Driver Families

Bucket

drivers/net

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/interrupt.h

Detected Declarations

• struct jme_spi_op
• struct dynpcc_info
• struct txdesc
• struct rxdesc
• struct jme_buffer_info
• struct jme_ring
• struct jme_adapter
• enum pci_dcsr_mrrs_vals
• enum pci_spi_bits
• enum jme_spi_op_bits
• enum pci_priv_pe1_bit_masks
• enum pci_priv_pe1_values
• enum dynamic_pcc_values
• enum jme_txdesc_flags_bits
• enum jme_txwbdesc_flags_bits
• enum jme_rxdesc_flags_bits
• enum jme_rxwbdesc_flags_bits
• enum jme_rxwbdesc_desccnt_mask
• enum jme_rxwbdesc_errstat_bits
• enum jme_flags_bits
• enum jme_iomap_offsets
• enum jme_iomap_lens
• enum jme_iomap_regs
• enum jme_txcs_bits
• enum jme_txcs_value
• enum jme_txmcs_bit_masks
• enum jme_txmcs_values
• enum jme_txpfc_bits_masks
• enum jme_txtrhd_bits_masks
• enum jme_txtrhd_shifts
• enum jme_txtrhd_values
• enum jme_rxcs_bit_masks
• enum jme_rxcs_values
• enum jme_rxmcs_bits
• enum jme_wfoi_bit_masks
• enum jme_wfoi_shifts
• enum jme_smi_bit_mask
• enum jme_smi_bit_shift
• enum jme_ghc_bit_mask
• enum jme_ghc_speed_val
• enum jme_ghc_to_clk
• enum jme_ghc_txmac_clk
• enum jme_pmcs_bit_masks
• enum jme_phy_pwr_bit_masks
• enum jme_phy_link_bit_mask
• enum jme_phy_link_speed_val
• enum jme_smbcsr_bit_mask
• enum jme_smbintf_bit_mask

Annotated Snippet

struct jme_spi_op {
	void __user *uwbuf;
	void __user *urbuf;
	__u8	wn;	/* Number of write actions */
	__u8	rn;	/* Number of read actions */
	__u8	bitn;	/* Number of bits per action */
	__u8	spd;	/* The maxim acceptable speed of controller, in MHz.*/
	__u8	mode;	/* CPOL, CPHA, and Duplex mode of SPI */

	/* Internal use only */
	u8	*kwbuf;
	u8	*krbuf;
	u8	sr;
	u16	halfclk; /* Half of clock cycle calculated from spd, in ns */
};

enum jme_spi_op_bits {
	SPI_MODE_CPHA	= 0x01,
	SPI_MODE_CPOL	= 0x02,
	SPI_MODE_DUP	= 0x80,
};

#define HALF_US 500	/* 500 ns */

#define PCI_PRIV_PE1		0xE4

enum pci_priv_pe1_bit_masks {
	PE1_ASPMSUPRT	= 0x00000003, /*
				       * RW:
				       * Aspm_support[1:0]
				       * (R/W Port of 5C[11:10])
				       */
	PE1_MULTIFUN	= 0x00000004, /* RW: Multi_fun_bit */
	PE1_RDYDMA	= 0x00000008, /* RO: ~link.rdy_for_dma */
	PE1_ASPMOPTL	= 0x00000030, /* RW: link.rx10s_option[1:0] */
	PE1_ASPMOPTH	= 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
	PE1_GPREG0	= 0x0000FF00, /*
				       * SRW:
				       * Cfg_gp_reg0
				       * [7:6] phy_giga BG control
				       * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
				       * [4:0] Reserved
				       */
	PE1_GPREG0_PBG	= 0x0000C000, /* phy_giga BG control */
	PE1_GPREG1	= 0x00FF0000, /* RW: Cfg_gp_reg1 */
	PE1_REVID	= 0xFF000000, /* RO: Rev ID */
};

enum pci_priv_pe1_values {
	PE1_GPREG0_ENBG		= 0x00000000, /* en BG */
	PE1_GPREG0_PDD3COLD	= 0x00004000, /* giga_PD + d3cold */
	PE1_GPREG0_PDPCIESD	= 0x00008000, /* giga_PD + pcie_shutdown */
	PE1_GPREG0_PDPCIEIDDQ	= 0x0000C000, /* giga_PD + pcie_iddq */
};

/*
 * Dynamic(adaptive)/Static PCC values
 */
enum dynamic_pcc_values {
	PCC_OFF		= 0,
	PCC_P1		= 1,
	PCC_P2		= 2,
	PCC_P3		= 3,

	PCC_OFF_TO	= 0,
	PCC_P1_TO	= 1,
	PCC_P2_TO	= 64,
	PCC_P3_TO	= 128,

	PCC_OFF_CNT	= 0,
	PCC_P1_CNT	= 1,
	PCC_P2_CNT	= 16,
	PCC_P3_CNT	= 32,
};
struct dynpcc_info {
	unsigned long	last_bytes;
	unsigned long	last_pkts;
	unsigned long	intr_cnt;
	unsigned char	cur;
	unsigned char	attempt;
	unsigned char	cnt;
};
#define PCC_INTERVAL_US	100000
#define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
#define PCC_P3_THRESHOLD (2 * 1024 * 1024)
#define PCC_P2_THRESHOLD 800
#define PCC_INTR_THRESHOLD 800
#define PCC_TX_TO 1000
#define PCC_TX_CNT 8

Annotation

• Immediate include surface: `linux/interrupt.h`.
• Detected declarations: `struct jme_spi_op`, `struct dynpcc_info`, `struct txdesc`, `struct rxdesc`, `struct jme_buffer_info`, `struct jme_ring`, `struct jme_adapter`, `enum pci_dcsr_mrrs_vals`, `enum pci_spi_bits`, `enum jme_spi_op_bits`.
• Atlas domain: Driver Families / drivers/net.
• Implementation status: source implementation candidate.
• Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.