drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/marvell/mvpp2/mvpp2_cls.c- Extension
.c- Size
- 50266 bytes
- Lines
- 1740
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
mvpp2.hmvpp2_cls.hmvpp2_prs.h
Detected Declarations
function mvpp2_cls_flow_hitsfunction mvpp2_cls_flow_readfunction mvpp2_cls_flow_writefunction mvpp2_cls_lookup_hitsfunction mvpp2_cls_lookup_readfunction mvpp2_cls_lookup_writefunction mvpp2_cls_flow_hek_num_getfunction mvpp2_cls_flow_hek_num_setfunction mvpp2_cls_flow_hek_getfunction mvpp2_cls_flow_hek_setfunction mvpp2_cls_flow_eng_setfunction mvpp2_cls_flow_eng_getfunction mvpp2_cls_flow_port_id_selfunction mvpp2_cls_flow_last_setfunction mvpp2_cls_flow_pri_setfunction mvpp2_cls_flow_port_addfunction mvpp2_cls_flow_port_removefunction mvpp2_cls_flow_lu_type_setfunction mvpp2_cls_flow_prs_initfunction mvpp2_cls_flow_lkp_initfunction mvpp2_cls_c2_writefunction mvpp2_cls_c2_readfunction mvpp2_cls_ethtool_flow_to_typefunction mvpp2_cls_c2_port_flow_indexfunction mvpp2_cls_flow_initfunction mvpp2_flow_add_hek_fieldfunction mvpp2_flow_set_hek_fieldsfunction for_each_set_bitfunction mvpp2_cls_hek_field_sizefunction flowfunction for_each_cls_flow_id_with_typefunction mvpp2_flow_get_hek_fieldsfunction mvpp2_port_rss_hash_opts_getfunction for_each_cls_flow_id_with_typefunction mvpp2_cls_port_init_flowsfunction mvpp2_port_c2_cls_initfunction mvpp2_cls_initfunction mvpp2_cls_port_configfunction mvpp2_cls_c2_hit_countfunction mvpp2_rss_port_c2_enablefunction mvpp2_rss_port_c2_disablefunction mvpp22_rss_ctxfunction mvpp22_port_rss_enablefunction mvpp22_port_rss_disablefunction mvpp22_port_c2_lookup_disablefunction mvpp2_cls_oversize_rxq_setfunction mvpp2_port_c2_tcam_rule_addfunction mvpp2_port_c2_rfs_rule_insert
Annotated Snippet
switch (BIT(i)) {
case MVPP22_CLS_HEK_OPT_MAC_DA:
field_id = MVPP22_CLS_FIELD_MAC_DA;
break;
case MVPP22_CLS_HEK_OPT_VLAN:
field_id = MVPP22_CLS_FIELD_VLAN;
break;
case MVPP22_CLS_HEK_OPT_VLAN_PRI:
field_id = MVPP22_CLS_FIELD_VLAN_PRI;
break;
case MVPP22_CLS_HEK_OPT_IP4SA:
field_id = MVPP22_CLS_FIELD_IP4SA;
break;
case MVPP22_CLS_HEK_OPT_IP4DA:
field_id = MVPP22_CLS_FIELD_IP4DA;
break;
case MVPP22_CLS_HEK_OPT_IP6SA:
field_id = MVPP22_CLS_FIELD_IP6SA;
break;
case MVPP22_CLS_HEK_OPT_IP6DA:
field_id = MVPP22_CLS_FIELD_IP6DA;
break;
case MVPP22_CLS_HEK_OPT_L4SIP:
field_id = MVPP22_CLS_FIELD_L4SIP;
break;
case MVPP22_CLS_HEK_OPT_L4DIP:
field_id = MVPP22_CLS_FIELD_L4DIP;
break;
default:
return -EINVAL;
}
if (mvpp2_flow_add_hek_field(fe, field_id))
return -EINVAL;
}
return 0;
}
/* Returns the size, in bits, of the corresponding HEK field */
static int mvpp2_cls_hek_field_size(u32 field)
{
switch (field) {
case MVPP22_CLS_HEK_OPT_MAC_DA:
return 48;
case MVPP22_CLS_HEK_OPT_VLAN:
return 12;
case MVPP22_CLS_HEK_OPT_VLAN_PRI:
return 3;
case MVPP22_CLS_HEK_OPT_IP4SA:
case MVPP22_CLS_HEK_OPT_IP4DA:
return 32;
case MVPP22_CLS_HEK_OPT_IP6SA:
case MVPP22_CLS_HEK_OPT_IP6DA:
return 128;
case MVPP22_CLS_HEK_OPT_L4SIP:
case MVPP22_CLS_HEK_OPT_L4DIP:
return 16;
default:
return -1;
}
}
const struct mvpp2_cls_flow *mvpp2_cls_flow_get(int flow)
{
if (flow >= MVPP2_N_PRS_FLOWS)
return NULL;
return &cls_flows[flow];
}
/* Set the hash generation options for the given traffic flow.
* One traffic flow (in the ethtool sense) has multiple classification flows,
* to handle specific cases such as fragmentation, or the presence of a
* VLAN / DSA Tag.
*
* Each of these individual flows has different constraints, for example we
* can't hash fragmented packets on L4 data (else we would risk having packet
* re-ordering), so each classification flows masks the options with their
* supported ones.
*
*/
static int mvpp2_port_rss_hash_opts_set(struct mvpp2_port *port, int flow_type,
u16 requested_opts)
{
const struct mvpp2_cls_flow *flow;
struct mvpp2_cls_flow_entry fe;
int i, engine, flow_index;
u16 hash_opts;
for_each_cls_flow_id_with_type(i, flow_type) {
Annotation
- Immediate include surface: `mvpp2.h`, `mvpp2_cls.h`, `mvpp2_prs.h`.
- Detected declarations: `function mvpp2_cls_flow_hits`, `function mvpp2_cls_flow_read`, `function mvpp2_cls_flow_write`, `function mvpp2_cls_lookup_hits`, `function mvpp2_cls_lookup_read`, `function mvpp2_cls_lookup_write`, `function mvpp2_cls_flow_hek_num_get`, `function mvpp2_cls_flow_hek_num_set`, `function mvpp2_cls_flow_hek_get`, `function mvpp2_cls_flow_hek_set`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.