drivers/net/ethernet/marvell/mvpp2/mvpp2.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/marvell/mvpp2/mvpp2.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/marvell/mvpp2/mvpp2.h
Extension
.h
Size
52960 bytes
Lines
1579
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mvpp2_rss_table {
	u32 indir[MVPP22_RSS_TABLE_ENTRIES];
};

struct mvpp2_buff_hdr {
	__le32 next_phys_addr;
	__le32 next_dma_addr;
	__le16 byte_count;
	__le16 info;
	__le16 reserved1;	/* bm_qset (for future use, BM) */
	u8 next_phys_addr_high;
	u8 next_dma_addr_high;
	__le16 reserved2;
	__le16 reserved3;
	__le16 reserved4;
	__le16 reserved5;
};

/* Shared Packet Processor resources */
struct mvpp2 {
	/* Shared registers' base addresses */
	void __iomem *lms_base;
	void __iomem *iface_base;
	void __iomem *cm3_base;

	/* On PPv2.2 and PPv2.3, each "software thread" can access the base
	 * register through a separate address space, each 64 KB apart
	 * from each other. Typically, such address spaces will be
	 * used per CPU.
	 */
	void __iomem *swth_base[MVPP2_MAX_THREADS];

	/* On PPv2.2 and PPv2.3, some port control registers are located into
	 * the system controller space. These registers are accessible
	 * through a regmap.
	 */
	struct regmap *sysctrl_base;

	/* Common clocks */
	struct clk *pp_clk;
	struct clk *gop_clk;
	struct clk *mg_clk;
	struct clk *mg_core_clk;
	struct clk *axi_clk;

	/* List of pointers to port structures */
	int port_count;
	struct mvpp2_port *port_list[MVPP2_MAX_PORTS];
	/* Map of enabled ports */
	unsigned long port_map;

	struct mvpp2_tai *tai;

	/* Number of Tx threads used */
	unsigned int nthreads;
	/* Map of threads needing locking */
	unsigned long lock_map;

	/* Aggregated TXQs */
	struct mvpp2_tx_queue *aggr_txqs;

	/* Are we using page_pool with per-cpu pools? */
	int percpu_pools;

	/* BM pools */
	struct mvpp2_bm_pool *bm_pools;

	/* PRS shadow table */
	struct mvpp2_prs_shadow *prs_shadow;
	/* PRS auxiliary table for double vlan entries control */
	bool *prs_double_vlans;

	/* Tclk value */
	u32 tclk;

	/* HW version */
	enum { MVPP21, MVPP22, MVPP23 } hw_version;

	/* Maximum number of RXQs per port */
	unsigned int max_port_rxqs;

	/* Workqueue to gather hardware statistics */
	char queue_name[31];
	struct workqueue_struct *stats_queue;

	/* Debugfs root entry */
	struct dentry *dbgfs_dir;

	/* Debugfs entries private data */
	struct mvpp2_dbgfs_entries *dbgfs_entries;

Annotation

Implementation Notes