drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/marvell/octeon_ep/octep_cnxk_pf.c
Extension
.c
Size
31730 bytes
Lines
968
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (!oct->mbox[vf_mbox_queue]) {
				dev_err(&oct->pdev->dev, "bad mbox vf %d\n", vf);
				continue;
			}
			schedule_work(&oct->mbox[vf_mbox_queue]->wk.work);
		}
		if (reg0)
			octep_write_csr64(oct, CNXK_SDP_EPF_MBOX_RINT(0), reg0);
	}
}

static irqreturn_t octep_pfvf_mbox_intr_handler_cnxk_pf(void *dev)
{
	struct octep_device *oct = (struct octep_device *)dev;

	octep_poll_pfvf_mailbox_cnxk_pf(oct);
	return IRQ_HANDLED;
}

/* Poll OEI events like heartbeat */
static void octep_poll_oei_cnxk_pf(struct octep_device *oct)
{
	u64 reg0;

	/* Check for OEI INTR */
	reg0 = octep_read_csr64(oct, CNXK_SDP_EPF_OEI_RINT);
	if (reg0) {
		octep_write_csr64(oct, CNXK_SDP_EPF_OEI_RINT, reg0);
		if (reg0 & CNXK_SDP_EPF_OEI_RINT_DATA_BIT_MBOX)
			queue_work(octep_wq, &oct->ctrl_mbox_task);
		if (reg0 & CNXK_SDP_EPF_OEI_RINT_DATA_BIT_HBEAT)
			atomic_set(&oct->hb_miss_cnt, 0);
	}
}

/* OEI interrupt handler */
static irqreturn_t octep_oei_intr_handler_cnxk_pf(void *dev)
{
	struct octep_device *oct = (struct octep_device *)dev;

	octep_poll_oei_cnxk_pf(oct);
	return IRQ_HANDLED;
}

/* Process non-ioq interrupts required to keep pf interface running.
 * OEI_RINT is needed for control mailbox
 * MBOX_RINT is needed for pfvf mailbox
 */
static void octep_poll_non_ioq_interrupts_cnxk_pf(struct octep_device *oct)
{
	octep_poll_pfvf_mailbox_cnxk_pf(oct);
	octep_poll_oei_cnxk_pf(oct);
}

/* Interrupt handler for input ring error interrupts. */
static irqreturn_t octep_ire_intr_handler_cnxk_pf(void *dev)
{
	struct octep_device *oct = (struct octep_device *)dev;
	struct pci_dev *pdev = oct->pdev;
	u64 reg_val = 0;
	int i = 0;

	/* Check for IRERR INTR */
	reg_val = octep_read_csr64(oct, CNXK_SDP_EPF_IRERR_RINT);
	if (reg_val) {
		dev_info(&pdev->dev,
			 "received IRERR_RINT intr: 0x%llx\n", reg_val);
		octep_write_csr64(oct, CNXK_SDP_EPF_IRERR_RINT, reg_val);

		for (i = 0; i < CFG_GET_PORTS_ACTIVE_IO_RINGS(oct->conf); i++) {
			reg_val = octep_read_csr64(oct,
						   CNXK_SDP_R_ERR_TYPE(i));
			if (reg_val) {
				dev_info(&pdev->dev,
					 "Received err type on IQ-%d: 0x%llx\n",
					 i, reg_val);
				octep_write_csr64(oct, CNXK_SDP_R_ERR_TYPE(i),
						  reg_val);
			}
		}
	}
	return IRQ_HANDLED;
}

/* Interrupt handler for output ring error interrupts. */
static irqreturn_t octep_ore_intr_handler_cnxk_pf(void *dev)
{
	struct octep_device *oct = (struct octep_device *)dev;
	struct pci_dev *pdev = oct->pdev;
	u64 reg_val = 0;

Annotation

Implementation Notes