drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/marvell/octeon_ep_vf/octep_vf_main.h
Extension
.h
Size
9802 bytes
Lines
339
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct octep_vf_mmio {
	/* The physical address to which the PCI address space is mapped. */
	u8 __iomem *hw_addr;

	/* Flag indicating the mapping was successful. */
	int mapped;
};

struct octep_vf_hw_ops {
	void (*setup_iq_regs)(struct octep_vf_device *oct, int q);
	int (*setup_oq_regs)(struct octep_vf_device *oct, int q);
	void (*setup_mbox_regs)(struct octep_vf_device *oct, int mbox);

	irqreturn_t (*non_ioq_intr_handler)(void *ioq_vector);
	irqreturn_t (*ioq_intr_handler)(void *ioq_vector);
	void (*reinit_regs)(struct octep_vf_device *oct);
	u32  (*update_iq_read_idx)(struct octep_vf_iq *iq);

	void (*enable_interrupts)(struct octep_vf_device *oct);
	void (*disable_interrupts)(struct octep_vf_device *oct);

	void (*enable_io_queues)(struct octep_vf_device *oct);
	void (*disable_io_queues)(struct octep_vf_device *oct);
	void (*enable_iq)(struct octep_vf_device *oct, int q);
	void (*disable_iq)(struct octep_vf_device *oct, int q);
	void (*enable_oq)(struct octep_vf_device *oct, int q);
	void (*disable_oq)(struct octep_vf_device *oct, int q);
	void (*reset_io_queues)(struct octep_vf_device *oct);
	void (*dump_registers)(struct octep_vf_device *oct);
};

/* Octeon mailbox data */
struct octep_vf_mbox_data {
	/* Holds the offset of received data via mailbox. */
	u32 data_index;

	/* Holds the received data via mailbox. */
	u8 recv_data[OCTEP_PFVF_MBOX_MAX_DATA_BUF_SIZE];
};

/* wrappers around work structs */
struct octep_vf_mbox_wk {
	struct work_struct work;
	void *ctxptr;
};

/* Octeon device mailbox */
struct octep_vf_mbox {
	/* A mutex to protect access to this q_mbox. */
	struct mutex lock;

	u32 state;

	/* SLI_MAC_PF_MBOX_INT for PF, SLI_PKT_MBOX_INT for VF. */
	u8 __iomem *mbox_int_reg;

	/* SLI_PKT_PF_VF_MBOX_SIG(0) for PF,
	 * SLI_PKT_PF_VF_MBOX_SIG(1) for VF.
	 */
	u8 __iomem *mbox_write_reg;

	/* SLI_PKT_PF_VF_MBOX_SIG(1) for PF,
	 * SLI_PKT_PF_VF_MBOX_SIG(0) for VF.
	 */
	u8 __iomem *mbox_read_reg;

	/* Octeon mailbox data */
	struct octep_vf_mbox_data mbox_data;

	/* Octeon mailbox work handler to process Mbox messages */
	struct octep_vf_mbox_wk wk;
};

/* Tx/Rx queue vector per interrupt. */
struct octep_vf_ioq_vector {
	char name[OCTEP_VF_MSIX_NAME_SIZE];
	struct napi_struct napi;
	struct octep_vf_device *octep_vf_dev;
	struct octep_vf_iq *iq;
	struct octep_vf_oq *oq;
	cpumask_t affinity_mask;
};

/* Octeon hardware/firmware offload capability flags. */
#define OCTEP_VF_CAP_TX_CHECKSUM BIT(0)
#define OCTEP_VF_CAP_RX_CHECKSUM BIT(1)
#define OCTEP_VF_CAP_TSO         BIT(2)

/* Link modes */
enum octep_vf_link_mode_bit_indices {

Annotation

Implementation Notes