drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/marvell/octeontx2/af/cn20k/mbox_init.c
Extension
.c
Size
12283 bytes
Lines
442
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

switch (intr_vec) {
		case RVU_MBOX_PF_INT_VEC_VFPF_MBOX0:
			irq_data[vec].intr_status =
						RVU_MBOX_PF_VFPF_INTX(0);
			irq_data[vec].start = 0;
			irq_data[vec].mdevs = 64;
			break;
		case RVU_MBOX_PF_INT_VEC_VFPF_MBOX1:
			irq_data[vec].intr_status =
						RVU_MBOX_PF_VFPF_INTX(1);
			irq_data[vec].start = 64;
			irq_data[vec].mdevs = 64;
			break;
		case RVU_MBOX_PF_INT_VEC_VFPF1_MBOX0:
			irq_data[vec].intr_status =
						RVU_MBOX_PF_VFPF1_INTX(0);
			irq_data[vec].start = 0;
			irq_data[vec].mdevs = 64;
			break;
		case RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1:
			irq_data[vec].intr_status = RVU_MBOX_PF_VFPF1_INTX(1);
			irq_data[vec].start = 64;
			irq_data[vec].mdevs = 64;
			break;
		}
		irq_data[vec].afvf_queue_work_hdlr =
						rvu_queue_work;
		offset = pf_vec_start + intr_vec;
		irq_data[vec].vec_num = offset;
		irq_data[vec].rvu = rvu;

		sprintf(&rvu->irq_name[offset * NAME_SIZE], "RVUAF VFAF%d Mbox%d",
			vec / 2, vec % 2);
		err = request_irq(pci_irq_vector(rvu->pdev, offset),
				  rvu->ng_rvu->rvu_mbox_ops->afvf_intr_handler, 0,
				  &rvu->irq_name[offset * NAME_SIZE],
				  &irq_data[vec]);
		if (err) {
			dev_err(rvu->dev,
				"RVUAF: IRQ registration failed for AFVF mbox irq\n");
			return err;
		}
		rvu->irq_allocated[offset] = true;
	}

	return 0;
}

/* CN20K mbox PFx => AF irq handler */
static irqreturn_t cn20k_mbox_pf_common_intr_handler(int irq, void *rvu_irq)
{
	struct rvu_irq_data *rvu_irq_data = rvu_irq;
	struct rvu *rvu = rvu_irq_data->rvu;
	u64 intr;

	/* Clear interrupts */
	intr = rvu_read64(rvu, BLKADDR_RVUM, rvu_irq_data->intr_status);
	rvu_write64(rvu, BLKADDR_RVUM, rvu_irq_data->intr_status, intr);

	if (intr)
		trace_otx2_msg_interrupt(rvu->pdev, "PF(s) to AF", intr);

	/* Sync with mbox memory region */
	rmb();

	rvu_irq_data->rvu_queue_work_hdlr(&rvu->afpf_wq_info,
					  rvu_irq_data->start,
					  rvu_irq_data->mdevs, intr);

	return IRQ_HANDLED;
}

void cn20k_rvu_enable_mbox_intr(struct rvu *rvu)
{
	struct rvu_hwinfo *hw = rvu->hw;

	/* Clear spurious irqs, if any */
	rvu_write64(rvu, BLKADDR_RVUM,
		    RVU_MBOX_AF_PFAF_INT(0), INTR_MASK(hw->total_pfs));

	rvu_write64(rvu, BLKADDR_RVUM,
		    RVU_MBOX_AF_PFAF_INT(1), INTR_MASK(hw->total_pfs - 64));

	rvu_write64(rvu, BLKADDR_RVUM,
		    RVU_MBOX_AF_PFAF1_INT(0), INTR_MASK(hw->total_pfs));

	rvu_write64(rvu, BLKADDR_RVUM,
		    RVU_MBOX_AF_PFAF1_INT(1), INTR_MASK(hw->total_pfs - 64));

	/* Enable mailbox interrupt for all PFs except PF0 i.e AF itself */

Annotation

Implementation Notes