drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/marvell/octeontx2/af/lmac_common.h- Extension
.h- Size
- 5570 bytes
- Lines
- 176
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
rvu.hcgx.h
Detected Declarations
struct lmacstruct mac_opsstruct cgx
Annotated Snippet
struct lmac {
wait_queue_head_t wq_cmd_cmplt;
/* Lock to serialize the command interface */
struct mutex cmd_lock;
u64 resp;
struct cgx_link_user_info link_info;
struct rsrc_bmap mac_to_index_bmap;
struct rsrc_bmap rx_fc_pfvf_bmap;
struct rsrc_bmap tx_fc_pfvf_bmap;
struct cgx_event_cb event_cb;
/* lock for serializing callback with unregister */
spinlock_t event_cb_lock;
struct cgx *cgx;
u8 mcast_filters_count;
u8 lmac_id;
u8 lmac_type;
bool cmd_pend;
char *name;
};
/* CGX & RPM has different feature set
* update the structure fields with different one
*/
struct mac_ops {
char *name;
/* Features like RXSTAT, TXSTAT, DMAC FILTER csrs differs by fixed
* bar offset for example
* CGX DMAC_CTL0 0x1f8
* RPM DMAC_CTL0 0x4ff8
*/
u64 csr_offset;
/* For ATF to send events to kernel, there is no dedicated interrupt
* defined hence CGX uses OVERFLOW bit in CMR_INT. RPM block supports
* SW_INT so that ATF triggers this interrupt after processing of
* requested command
*/
u64 int_register;
u64 int_set_reg;
/* lmac offset is different is RPM */
u8 lmac_offset;
u8 irq_offset;
u8 int_ena_bit;
u8 lmac_fwi;
bool non_contiguous_serdes_lane;
/* RPM & CGX differs in number of Receive/transmit stats */
u8 rx_stats_cnt;
u8 tx_stats_cnt;
/* Unlike CN10K which shares same CSR offset with CGX
* CNF10KB has different csr offset
*/
u64 rxid_map_offset;
u8 dmac_filter_count;
/* Incase of RPM get number of lmacs from RPMX_CMR_RX_LMACS[LMAC_EXIST]
* number of setbits in lmac_exist tells number of lmacs
*/
int (*get_nr_lmacs)(void *cgx);
u8 (*get_lmac_type)(void *cgx, int lmac_id);
u32 (*lmac_fifo_len)(void *cgx, int lmac_id);
int (*mac_lmac_intl_lbk)(void *cgx, int lmac_id,
bool enable);
/* Register Stats related functions */
int (*mac_get_rx_stats)(void *cgx, int lmac_id,
int idx, u64 *rx_stat);
int (*mac_get_tx_stats)(void *cgx, int lmac_id,
int idx, u64 *tx_stat);
/* Enable LMAC Pause Frame Configuration */
void (*mac_enadis_rx_pause_fwding)(void *cgxd,
int lmac_id,
bool enable);
int (*mac_get_pause_frm_status)(void *cgxd,
int lmac_id,
u8 *tx_pause,
u8 *rx_pause);
int (*mac_enadis_pause_frm)(void *cgxd,
int lmac_id,
u8 tx_pause,
u8 rx_pause);
void (*mac_pause_frm_config)(void *cgxd,
int lmac_id,
bool enable);
/* Enable/Disable Inbound PTP */
void (*mac_enadis_ptp_config)(void *cgxd,
int lmac_id,
bool enable);
Annotation
- Immediate include surface: `rvu.h`, `cgx.h`.
- Detected declarations: `struct lmac`, `struct mac_ops`, `struct cgx`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.