drivers/net/ethernet/marvell/octeontx2/af/mbox.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/marvell/octeontx2/af/mbox.h- Extension
.h- Size
- 70349 bytes
- Lines
- 2646
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/etherdevice.hlinux/sizes.hlinux/ethtool.hrvu_struct.hcommon.hcn20k/struct.h
Detected Declarations
struct otx2_mbox_devstruct otx2_mboxstruct mbox_hdrstruct mbox_msghdrstruct msg_reqstruct msg_rspstruct ready_msg_rspstruct rsrc_attachstruct rsrc_detachstruct free_rsrcs_rspstruct msix_offset_rspstruct get_hw_cap_rspstruct cgx_stats_rspstruct cgx_fec_stats_rspstruct cgx_mac_addr_set_or_getstruct cgx_mac_addr_add_reqstruct cgx_mac_addr_add_rspstruct cgx_mac_addr_del_reqstruct cgx_max_dmac_entries_get_rspstruct cgx_link_user_infostruct cgx_link_info_msgstruct cgx_pause_frm_cfgstruct fec_modestruct sfp_eeprom_sstruct phy_sstruct fec_stats_sstruct cgx_lmac_fwdata_sstruct cgx_fw_datastruct cgx_set_link_mode_argsstruct cgx_set_link_mode_reqstruct cgx_set_link_mode_rspstruct cgx_mac_addr_reset_reqstruct cgx_mac_addr_update_reqstruct cgx_mac_addr_update_rspstruct cgx_features_info_msgstruct rpm_stats_rspstruct cgx_pfc_cfgstruct cgx_pfc_rspstruct npc_set_pkindstruct npa_lf_alloc_reqstruct npa_lf_alloc_rspstruct npa_aq_enq_reqstruct npa_aq_enq_rspstruct npa_cn20k_aq_enq_reqstruct npa_cn20k_aq_enq_rspstruct hwctx_disable_reqstruct nix_lf_alloc_reqstruct nix_lf_alloc_rsp
Annotated Snippet
struct otx2_mbox_dev {
void *mbase; /* This dev's mbox region */
void *hwbase;
spinlock_t mbox_lock;
u16 msg_size; /* Total msg size to be sent */
u16 rsp_size; /* Total rsp size to be sure the reply is ok */
u16 num_msgs; /* No of msgs sent or waiting for response */
u16 msgs_acked; /* No of msgs for which response is received */
};
struct otx2_mbox {
struct pci_dev *pdev;
void *hwbase; /* Mbox region advertised by HW */
void *reg_base;/* CSR base for this dev */
u64 trigger; /* Trigger mbox notification */
u16 tr_shift; /* Mbox trigger shift */
u64 rx_start; /* Offset of Rx region in mbox memory */
u64 tx_start; /* Offset of Tx region in mbox memory */
u16 rx_size; /* Size of Rx region */
u16 tx_size; /* Size of Tx region */
u16 ndevs; /* The number of peers */
struct otx2_mbox_dev *dev;
};
/* Header which precedes all mbox messages */
struct mbox_hdr {
u64 msg_size; /* Total msgs size embedded */
u16 num_msgs; /* No of msgs embedded */
u16 opt_msg;
u8 sig;
};
/* Header which precedes every msg and is also part of it */
struct mbox_msghdr {
u16 pcifunc; /* Who's sending this msg */
u16 id; /* Mbox message ID */
#define OTX2_MBOX_REQ_SIG (0xdead)
#define OTX2_MBOX_RSP_SIG (0xbeef)
u16 sig; /* Signature, for validating corrupted msgs */
#define OTX2_MBOX_VERSION (0x000a)
u16 ver; /* Version of msg's structure for this ID */
u16 next_msgoff; /* Offset of next msg within mailbox region */
int rc; /* Msg process'ed response code */
};
void otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid);
void otx2_mbox_destroy(struct otx2_mbox *mbox);
int otx2_mbox_init(struct otx2_mbox *mbox, void __force *hwbase,
struct pci_dev *pdev, void __force *reg_base,
int direction, int ndevs);
int otx2_mbox_regions_init(struct otx2_mbox *mbox, void __force **hwbase,
struct pci_dev *pdev, void __force *reg_base,
int direction, int ndevs, unsigned long *bmap);
void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid);
void otx2_mbox_msg_send_up(struct otx2_mbox *mbox, int devid);
int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid);
int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid);
struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
int size, int size_rsp);
struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
struct mbox_msghdr *msg);
int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid);
int otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid,
u16 pcifunc, u16 id);
bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid);
const char *otx2_mbox_id2name(u16 id);
static inline struct mbox_msghdr *otx2_mbox_alloc_msg(struct otx2_mbox *mbox,
int devid, int size)
{
return otx2_mbox_alloc_msg_rsp(mbox, devid, size, 0);
}
bool otx2_mbox_wait_for_zero(struct otx2_mbox *mbox, int devid);
/* Mailbox message types */
#define MBOX_MSG_MASK 0xFFFF
#define MBOX_MSG_INVALID 0xFFFE
#define MBOX_MSG_MAX 0xFFFF
#define MBOX_MESSAGES \
/* Generic mbox IDs (range 0x000 - 0x1FF) */ \
M(READY, 0x001, ready, msg_req, ready_msg_rsp) \
M(ATTACH_RESOURCES, 0x002, attach_resources, rsrc_attach, msg_rsp) \
M(DETACH_RESOURCES, 0x003, detach_resources, rsrc_detach, msg_rsp) \
M(FREE_RSRC_CNT, 0x004, free_rsrc_cnt, msg_req, free_rsrcs_rsp) \
M(MSIX_OFFSET, 0x005, msix_offset, msg_req, msix_offset_rsp) \
M(VF_FLR, 0x006, vf_flr, msg_req, msg_rsp) \
M(PTP_OP, 0x007, ptp_op, ptp_req, ptp_rsp) \
Annotation
- Immediate include surface: `linux/etherdevice.h`, `linux/sizes.h`, `linux/ethtool.h`, `rvu_struct.h`, `common.h`, `cn20k/struct.h`.
- Detected declarations: `struct otx2_mbox_dev`, `struct otx2_mbox`, `struct mbox_hdr`, `struct mbox_msghdr`, `struct msg_req`, `struct msg_rsp`, `struct ready_msg_rsp`, `struct rsrc_attach`, `struct rsrc_detach`, `struct free_rsrcs_rsp`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.