drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/marvell/octeontx2/af/rvu_cgx.c- Extension
.c- Size
- 35366 bytes
- Lines
- 1358
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/types.hlinux/module.hlinux/pci.hrvu.hcgx.hlmac_common.hrvu_reg.hrvu_trace.hrvu_npc_hash.h
Detected Declarations
struct cgx_evq_entryfunction is_mac_feature_supportedfunction cgxlmac_to_pfmapfunction cgxlmac_to_pffunction cgxlmac_id_to_bmapfunction rvu_map_cgx_nix_blockfunction rvu_map_cgx_lmac_pffunction for_each_set_bitfunction rvu_cgx_send_link_infofunction cgx_lmac_posteventfunction cgx_notify_pfsfunction cgx_evhandler_taskfunction cgx_lmac_event_handler_initfunction for_each_set_bitfunction rvu_cgx_wq_destroyfunction rvu_cgx_initfunction cgx_start_linkupfunction rvu_cgx_exitfunction is_cgx_config_permittedfunction rvu_cgx_enadis_rx_bpfunction rvu_cgx_config_rxtxfunction rvu_cgx_tx_enablefunction rvu_cgx_config_txfunction rvu_cgx_disable_dmac_entriesfunction rvu_mbox_handler_cgx_start_rxtxfunction rvu_mbox_handler_cgx_stop_rxtxfunction rvu_lmac_get_statsfunction rvu_mbox_handler_cgx_statsfunction rvu_mbox_handler_rpm_statsfunction rvu_mbox_handler_cgx_stats_rstfunction rvu_mbox_handler_cgx_fec_statsfunction rvu_mbox_handler_cgx_mac_addr_setfunction rvu_mbox_handler_cgx_mac_addr_addfunction rvu_mbox_handler_cgx_mac_addr_delfunction rvu_mbox_handler_cgx_mac_max_entries_getfunction rvu_mbox_handler_cgx_mac_addr_getfunction rvu_mbox_handler_cgx_promisc_enablefunction rvu_mbox_handler_cgx_promisc_disablefunction rvu_cgx_ptp_rx_cfgfunction rvu_mbox_handler_cgx_ptp_rx_enablefunction rvu_mbox_handler_cgx_ptp_rx_disablefunction rvu_cgx_config_linkeventsfunction rvu_mbox_handler_cgx_start_linkeventsfunction rvu_mbox_handler_cgx_stop_linkeventsfunction rvu_mbox_handler_cgx_get_linkinfofunction rvu_mbox_handler_cgx_features_getfunction rvu_cgx_get_fifolenfunction rvu_cgx_get_lmac_fifolen
Annotated Snippet
struct cgx_evq_entry {
struct list_head evq_node;
struct cgx_link_event link_event;
};
#define M(_name, _id, _fn_name, _req_type, _rsp_type) \
static struct _req_type __maybe_unused \
*otx2_mbox_alloc_msg_ ## _fn_name(struct rvu *rvu, int devid) \
{ \
struct _req_type *req; \
\
req = (struct _req_type *)otx2_mbox_alloc_msg_rsp( \
&rvu->afpf_wq_info.mbox_up, devid, sizeof(struct _req_type), \
sizeof(struct _rsp_type)); \
if (!req) \
return NULL; \
req->hdr.sig = OTX2_MBOX_REQ_SIG; \
req->hdr.id = _id; \
trace_otx2_msg_alloc(rvu->pdev, _id, sizeof(*req), 0); \
return req; \
}
MBOX_UP_CGX_MESSAGES
#undef M
bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature)
{
u8 cgx_id, lmac_id;
void *cgxd;
if (!is_pf_cgxmapped(rvu, pf))
return 0;
rvu_get_cgx_lmac_id(rvu->pf2cgxlmac_map[pf], &cgx_id, &lmac_id);
cgxd = rvu_cgx_pdata(cgx_id, rvu);
return (cgx_features_get(cgxd) & feature);
}
#define CGX_OFFSET(x) ((x) * rvu->hw->lmac_per_cgx)
/* Returns bitmap of mapped PFs */
static u64 cgxlmac_to_pfmap(struct rvu *rvu, u8 cgx_id, u8 lmac_id)
{
return rvu->cgxlmac2pf_map[CGX_OFFSET(cgx_id) + lmac_id];
}
int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id)
{
unsigned long pfmap;
pfmap = cgxlmac_to_pfmap(rvu, cgx_id, lmac_id);
/* Assumes only one pf mapped to a cgx lmac port */
if (!pfmap)
return -ENODEV;
else
return find_first_bit(&pfmap,
rvu->cgx_cnt_max * rvu->hw->lmac_per_cgx);
}
static u8 cgxlmac_id_to_bmap(u8 cgx_id, u8 lmac_id)
{
return ((cgx_id & 0xF) << 4) | (lmac_id & 0xF);
}
void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu)
{
if (cgx_id >= rvu->cgx_cnt_max)
return NULL;
return rvu->cgx_idmap[cgx_id];
}
/* Return first enabled CGX instance if none are enabled then return NULL */
void *rvu_first_cgx_pdata(struct rvu *rvu)
{
int first_enabled_cgx = 0;
void *cgxd = NULL;
for (; first_enabled_cgx < rvu->cgx_cnt_max; first_enabled_cgx++) {
cgxd = rvu_cgx_pdata(first_enabled_cgx, rvu);
if (cgxd)
break;
}
return cgxd;
}
/* Based on P2X connectivity find mapped NIX block for a PF */
static void rvu_map_cgx_nix_block(struct rvu *rvu, int pf,
Annotation
- Immediate include surface: `linux/types.h`, `linux/module.h`, `linux/pci.h`, `rvu.h`, `cgx.h`, `lmac_common.h`, `rvu_reg.h`, `rvu_trace.h`.
- Detected declarations: `struct cgx_evq_entry`, `function is_mac_feature_supported`, `function cgxlmac_to_pfmap`, `function cgxlmac_to_pf`, `function cgxlmac_id_to_bmap`, `function rvu_map_cgx_nix_block`, `function rvu_map_cgx_lmac_pf`, `function for_each_set_bit`, `function rvu_cgx_send_link_info`, `function cgx_lmac_postevent`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.