drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/marvell/octeontx2/af/rvu_cpt.c
Extension
.c
Size
35639 bytes
Lines
1320
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

switch (vec) {
		case 0:
			eng = i;
			break;
		case 1:
			eng = i + 64;
			break;
		case 2:
			eng = i + 128;
			break;
		}
		grp = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_CTL2(eng)) & 0xFF;
		/* Disable and enable the engine which triggers fault */
		rvu_write64(rvu, blkaddr, CPT_AF_EXEX_CTL2(eng), 0x0);
		val = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_CTL(eng));
		rvu_write64(rvu, blkaddr, CPT_AF_EXEX_CTL(eng), val & ~1ULL);

		rvu_write64(rvu, blkaddr, CPT_AF_EXEX_CTL2(eng), grp);
		rvu_write64(rvu, blkaddr, CPT_AF_EXEX_CTL(eng), val | 1ULL);

		spin_lock(&rvu->cpt_intr_lock);
		block->cpt_flt_eng_map[vec] |= BIT_ULL(i);
		val = rvu_read64(rvu, blkaddr, CPT_AF_EXEX_STS(eng));
		val = val & 0x3;
		if (val == 0x1 || val == 0x2)
			block->cpt_rcvrd_eng_map[vec] |= BIT_ULL(i);
		spin_unlock(&rvu->cpt_intr_lock);
	}
	rvu_write64(rvu, blkaddr, CPT_AF_FLTX_INT(vec), reg);

	return IRQ_HANDLED;
}

static irqreturn_t rvu_cpt_af_flt0_intr_handler(int irq, void *ptr)
{
	return cpt_af_flt_intr_handler(CPT_AF_INT_VEC_FLT0, ptr);
}

static irqreturn_t rvu_cpt_af_flt1_intr_handler(int irq, void *ptr)
{
	return cpt_af_flt_intr_handler(CPT_AF_INT_VEC_FLT1, ptr);
}

static irqreturn_t rvu_cpt_af_flt2_intr_handler(int irq, void *ptr)
{
	return cpt_af_flt_intr_handler(CPT_10K_AF_INT_VEC_FLT2, ptr);
}

static irqreturn_t rvu_cpt_af_rvu_intr_handler(int irq, void *ptr)
{
	struct rvu_block *block = ptr;
	struct rvu *rvu = block->rvu;
	int blkaddr = block->addr;
	u64 reg;

	reg = rvu_read64(rvu, blkaddr, CPT_AF_RVU_INT);
	dev_err_ratelimited(rvu->dev, "Received CPTAF RVU irq : 0x%llx", reg);

	rvu_write64(rvu, blkaddr, CPT_AF_RVU_INT, reg);
	return IRQ_HANDLED;
}

static irqreturn_t rvu_cpt_af_ras_intr_handler(int irq, void *ptr)
{
	struct rvu_block *block = ptr;
	struct rvu *rvu = block->rvu;
	int blkaddr = block->addr;
	u64 reg;

	reg = rvu_read64(rvu, blkaddr, CPT_AF_RAS_INT);
	dev_err_ratelimited(rvu->dev, "Received CPTAF RAS irq : 0x%llx", reg);

	rvu_write64(rvu, blkaddr, CPT_AF_RAS_INT, reg);
	return IRQ_HANDLED;
}

static int rvu_cpt_do_register_interrupt(struct rvu_block *block, int irq_offs,
					 irq_handler_t handler,
					 const char *name)
{
	struct rvu *rvu = block->rvu;
	int ret;

	ret = request_irq(pci_irq_vector(rvu->pdev, irq_offs), handler, 0,
			  name, block);
	if (ret) {
		dev_err(rvu->dev, "RVUAF: %s irq registration failed", name);
		return ret;
	}

Annotation

Implementation Notes