drivers/net/ethernet/marvell/octeontx2/af/rvu.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/marvell/octeontx2/af/rvu.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/marvell/octeontx2/af/rvu.h- Extension
.h- Size
- 36037 bytes
- Lines
- 1200
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/pci.hnet/devlink.hlinux/soc/marvell/silicons.hrvu_struct.hrvu_devlink.hcommon.hmbox.hnpc.hrvu_reg.hptp.h
Detected Declarations
struct dump_ctxstruct cpt_ctxstruct rvu_debugfsstruct rvu_workstruct rsrc_bmapstruct rvu_blockstruct nix_mcaststruct nix_mce_liststruct nix_mcast_grp_elemstruct nix_mcast_grpstruct npc_layer_mdatastruct npc_key_fieldstruct npc_mcamstruct rvu_pfvfstruct nix_bpstruct nix_txschstruct nix_mark_formatstruct nix_smq_tree_ctxstruct nix_smq_flush_ctxstruct npc_pkindstruct nix_flowkeystruct nix_lsostruct nix_txvlanstruct nix_ipolicerstruct nix_hwstruct hw_capstruct rvu_hwinfostruct mbox_wq_infostruct rvu_irq_datastruct mbox_opsstruct channel_fwdatastruct altaf_intr_notifystruct rvu_fwdatastruct ptpstruct npc_kpu_profile_adapterstruct rvu_switchstruct rep_evtq_entstruct rvuenum rvu_pfvf_flagsenum regmap_blockfunction Copyrightfunction rvu_pcifunc_pf_maskfunction rvu_write64function rvu_read64function rvupf_write64function rvupf_read64function rvu_bar2_sel_write64function is_rvu_pre_96xx_C0
Annotated Snippet
struct dump_ctx {
int lf;
int id;
bool all;
};
struct cpt_ctx {
int blkaddr;
struct rvu *rvu;
};
struct rvu_debugfs {
struct dentry *root;
struct dentry *cgx_root;
struct dentry *cgx;
struct dentry *lmac;
struct dentry *npa;
struct dentry *nix;
struct dentry *npc;
struct dentry *cpt;
struct dentry *mcs_root;
struct dentry *mcs;
struct dentry *mcs_rx;
struct dentry *mcs_tx;
struct dump_ctx npa_aura_ctx;
struct dump_ctx npa_pool_ctx;
struct dump_ctx nix_cq_ctx;
struct dump_ctx nix_rq_ctx;
struct dump_ctx nix_sq_ctx;
struct dump_ctx nix_tm_ctx;
struct cpt_ctx cpt_ctx[MAX_CPT_BLKS];
int npa_qsize_id;
int nix_qsize_id;
};
#endif
struct rvu_work {
struct work_struct work;
struct rvu *rvu;
int num_msgs;
int up_num_msgs;
};
struct rsrc_bmap {
unsigned long *bmap; /* Pointer to resource bitmap */
u16 max; /* Max resource id or count */
};
struct rvu_block {
struct rsrc_bmap lf;
struct admin_queue *aq; /* NIX/NPA AQ */
u16 *fn_map; /* LF to pcifunc mapping */
bool multislot;
bool implemented;
u8 addr; /* RVU_BLOCK_ADDR_E */
u8 type; /* RVU_BLOCK_TYPE_E */
u8 lfshift;
u64 lookup_reg;
u64 pf_lfcnt_reg;
u64 vf_lfcnt_reg;
u64 lfcfg_reg;
u64 msixcfg_reg;
u64 lfreset_reg;
unsigned char name[NAME_SIZE];
struct rvu *rvu;
u64 cpt_flt_eng_map[3];
u64 cpt_rcvrd_eng_map[3];
};
struct nix_mcast {
struct qmem *mce_ctx;
struct qmem *mcast_buf;
int replay_pkind;
struct rsrc_bmap mce_counter[2];
/* Counters for both ingress and egress mcast lists */
struct mutex mce_lock; /* Serialize MCE updates */
};
struct nix_mce_list {
struct hlist_head head;
int count;
int max;
};
struct nix_mcast_grp_elem {
struct nix_mce_list mcast_mce_list;
u32 mcast_grp_idx;
u32 pcifunc;
int mcam_index;
int mce_start_index;
Annotation
- Immediate include surface: `linux/pci.h`, `net/devlink.h`, `linux/soc/marvell/silicons.h`, `rvu_struct.h`, `rvu_devlink.h`, `common.h`, `mbox.h`, `npc.h`.
- Detected declarations: `struct dump_ctx`, `struct cpt_ctx`, `struct rvu_debugfs`, `struct rvu_work`, `struct rsrc_bmap`, `struct rvu_block`, `struct nix_mcast`, `struct nix_mce_list`, `struct nix_mcast_grp_elem`, `struct nix_mcast_grp`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.