drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h

File Facts

System

Linux kernel

Corpus path

drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h

Extension

.h

Size

23564 bytes

Lines

880

Domain

Driver Families

Bucket

drivers/net

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• No C-style include directives detected by the generator.

Detected Declarations

• struct npa_aq_inst_s
• struct npa_aq_res_s
• struct npa_aura_s
• struct npa_pool_s
• struct nix_aq_inst_s
• struct nix_aq_res_s
• struct nix_cq_ctx_s
• struct nix_cn10k_rq_ctx_s
• struct nix_cn10k_sq_ctx_s
• struct nix_rq_ctx_s
• struct nix_sq_ctx_s
• struct nix_rsse_s
• struct nix_rx_mce_s
• struct nix_bandprof_s
• struct nix_lso_format
• struct nix_rx_flowkey_alg
• enum rvu_block_addr_e
• enum rvu_block_type_e
• enum rvu_af_int_vec_e
• enum cpt_af_int_vec_e
• enum cpt_cn10k_flt_int_vec_e
• enum npa_af_int_vec_e
• enum nix_af_int_vec_e
• enum rvu_pf_int_vec_e
• enum npa_aq_comp
• enum npa_aq_ctype
• enum npa_aq_instop
• enum npa_inpq
• enum nix_aq_comp
• enum nix_aq_ctype
• enum nix_aq_instop
• enum nix_maxsqesz
• enum nix_stype
• enum nix_band_prof_layers
• enum NIX_RX_BAND_PROF_ACTIONRESULT_E
• enum nix_band_prof_pc_mode
• enum nix_lsoalg
• enum nix_txlayer
• enum nix_vtag_size
• enum nix_tx_vtag_op
• enum nix_stat_lf_tx
• enum nix_stat_lf_rx

Annotated Snippet

struct npa_aq_inst_s {
	u64 op                    : 4; /* W0 */
	u64 ctype                 : 4;
	u64 lf                    : 9;
	u64 reserved_17_23        : 7;
	u64 cindex                : 20;
	u64 reserved_44_62        : 19;
	u64 doneint               : 1;
	u64 res_addr;			/* W1 */
};

/* NPA admin queue result structure */
struct npa_aq_res_s {
	u64 op                    : 4; /* W0 */
	u64 ctype                 : 4;
	u64 compcode              : 8;
	u64 doneint               : 1;
	u64 reserved_17_63        : 47;
	u64 reserved_64_127;		/* W1 */
};

struct npa_aura_s {
	u64 pool_addr;			/* W0 */
	u64 ena                   : 1;  /* W1 */
	u64 reserved_65           : 2;
	u64 pool_caching          : 1;
	u64 pool_way_mask         : 16;
	u64 avg_con               : 9;
	u64 reserved_93           : 1;
	u64 pool_drop_ena         : 1;
	u64 aura_drop_ena         : 1;
	u64 bp_ena                : 2;
	u64 reserved_98_103       : 6;
	u64 aura_drop             : 8;
	u64 shift                 : 6;
	u64 reserved_118_119      : 2;
	u64 avg_level             : 8;
	u64 count                 : 36; /* W2 */
	u64 reserved_164_167      : 4;
	u64 nix0_bpid             : 9;
	u64 reserved_177_179      : 3;
	u64 nix1_bpid             : 9;
	u64 reserved_189_191      : 3;
	u64 limit                 : 36; /* W3 */
	u64 reserved_228_231      : 4;
	u64 bp                    : 8;
	u64 reserved_241_243      : 3;
	u64 fc_be                 : 1;
	u64 fc_ena                : 1;
	u64 fc_up_crossing        : 1;
	u64 fc_stype              : 2;
	u64 fc_hyst_bits          : 4;
	u64 reserved_252_255      : 4;
	u64 fc_addr;			/* W4 */
	u64 pool_drop             : 8;  /* W5 */
	u64 update_time           : 16;
	u64 err_int               : 8;
	u64 err_int_ena           : 8;
	u64 thresh_int            : 1;
	u64 thresh_int_ena        : 1;
	u64 thresh_up             : 1;
	u64 reserved_363          : 1;
	u64 thresh_qint_idx       : 7;
	u64 reserved_371          : 1;
	u64 err_qint_idx          : 7;
	u64 reserved_379_383      : 5;
	u64 thresh                : 36; /* W6*/
	u64 rsvd_423_420          : 4;
	u64 fc_msh_dst            : 11;
	u64 reserved_435_447      : 13;
	u64 reserved_448_511;		/* W7 */
};

struct npa_pool_s {
	u64 stack_base;			/* W0 */
	u64 ena                   : 1;
	u64 nat_align             : 1;
	u64 reserved_66_67        : 2;
	u64 stack_caching         : 1;
	u64 reserved_70_71        : 3;
	u64 stack_way_mask        : 16;
	u64 buf_offset            : 12;
	u64 reserved_100_103      : 4;
	u64 buf_size              : 11;
	u64 reserved_115_127      : 13;
	u64 stack_max_pages       : 32;
	u64 stack_pages           : 32;
	u64 op_pc                 : 48;
	u64 reserved_240_255      : 16;
	u64 stack_offset          : 4;

Annotation

• Detected declarations: `struct npa_aq_inst_s`, `struct npa_aq_res_s`, `struct npa_aura_s`, `struct npa_pool_s`, `struct nix_aq_inst_s`, `struct nix_aq_res_s`, `struct nix_cq_ctx_s`, `struct nix_cn10k_rq_ctx_s`, `struct nix_cn10k_sq_ctx_s`, `struct nix_rq_ctx_s`.
• Atlas domain: Driver Families / drivers/net.
• Implementation status: source implementation candidate.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.