drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/marvell/octeontx2/nic/cn10k_ipsec.h
Extension
.h
Size
7008 bytes
Lines
266
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct cn10k_cpt_inst_queue {
	u8 *vaddr;
	u8 *real_vaddr;
	dma_addr_t dma_addr;
	dma_addr_t real_dma_addr;
	u32 size;
};

enum cn10k_cpt_hw_state_e {
	CN10K_CPT_HW_UNAVAILABLE,
	CN10K_CPT_HW_AVAILABLE,
	CN10K_CPT_HW_IN_USE
};

struct cn10k_ipsec {
	/* Outbound CPT */
	u64 io_addr;
	atomic_t cpt_state;
	struct cn10k_cpt_inst_queue iq;

	/* SA info */
	u32 sa_size;
	u32 outb_sa_count;
	struct work_struct sa_work;
	struct workqueue_struct *sa_workq;
};

/* CN10K IPSEC Security Association (SA) */
/* SA direction */
#define CN10K_IPSEC_SA_DIR_INB			0
#define CN10K_IPSEC_SA_DIR_OUTB			1
/* SA protocol */
#define CN10K_IPSEC_SA_IPSEC_PROTO_AH		0
#define CN10K_IPSEC_SA_IPSEC_PROTO_ESP		1
/* SA Encryption Type */
#define CN10K_IPSEC_SA_ENCAP_TYPE_AES_GCM	5
/* SA IPSEC mode Transport/Tunnel */
#define CN10K_IPSEC_SA_IPSEC_MODE_TRANSPORT	0
#define CN10K_IPSEC_SA_IPSEC_MODE_TUNNEL	1
/* SA AES Key Length */
#define CN10K_IPSEC_SA_AES_KEY_LEN_128		1
#define CN10K_IPSEC_SA_AES_KEY_LEN_192		2
#define CN10K_IPSEC_SA_AES_KEY_LEN_256		3
/* IV Source */
#define CN10K_IPSEC_SA_IV_SRC_COUNTER		0
#define CN10K_IPSEC_SA_IV_SRC_PACKET		3

struct cn10k_tx_sa_s {
	u64 esn_en		: 1; /* W0 */
	u64 rsvd_w0_1_8		: 8;
	u64 hw_ctx_off		: 7;
	u64 ctx_id		: 16;
	u64 rsvd_w0_32_47	: 16;
	u64 ctx_push_size	: 7;
	u64 rsvd_w0_55		: 1;
	u64 ctx_hdr_size	: 2;
	u64 aop_valid		: 1;
	u64 rsvd_w0_59		: 1;
	u64 ctx_size		: 4;
	u64 w1;			/* W1 */
	u64 sa_valid		: 1; /* W2 */
	u64 sa_dir		: 1;
	u64 rsvd_w2_2_3		: 2;
	u64 ipsec_mode		: 1;
	u64 ipsec_protocol	: 1;
	u64 aes_key_len		: 2;
	u64 enc_type		: 3;
	u64 rsvd_w2_11_19	: 9;
	u64 iv_src		: 2;
	u64 rsvd_w2_22_31	: 10;
	u64 rsvd_w2_32_63	: 32;
	u64 w3;			/* W3 */
	u8 cipher_key[32];	/* W4 - W7 */
	u32 rsvd_w8_0_31;	/* W8 : IV */
	u32 iv_gcm_salt;
	u64 rsvd_w9_w30[22];	/* W9 - W30 */
	u64 hw_ctx[6];		/* W31 - W36 */
};

/* CPT instruction parameter-1 */
#define CN10K_IPSEC_INST_PARAM1_DIS_L4_CSUM		0x1
#define CN10K_IPSEC_INST_PARAM1_DIS_L3_CSUM		0x2
#define CN10K_IPSEC_INST_PARAM1_CRYPTO_MODE		0x20
#define CN10K_IPSEC_INST_PARAM1_IV_OFFSET_SHIFT		8

/* CPT instruction parameter-2 */
#define CN10K_IPSEC_INST_PARAM2_ENC_DATA_OFFSET_SHIFT	0
#define CN10K_IPSEC_INST_PARAM2_AUTH_DATA_OFFSET_SHIFT	8

/* CPT Instruction Structure */

Annotation

Implementation Notes