drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/marvell/octeontx2/nic/otx2_txrx.c- Extension
.c- Size
- 41164 bytes
- Lines
- 1585
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: exported/initcall integration point
- Status
- integration implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Exports symbols or registers init work; inspect boot/module ordering and who consumes the exported contract.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/etherdevice.hnet/ip.hnet/tso.hlinux/bpf.hlinux/bpf_trace.hnet/ip6_checksum.hnet/xfrm.hnet/xdp.hotx2_reg.hotx2_common.hotx2_struct.hotx2_txrx.hotx2_ptp.hcn10k.hotx2_xsk.h
Detected Declarations
function otx2_get_free_sqefunction otx2_sq_set_sqe_basefunction otx2_nix_cq_op_statusfunction frag_numfunction otx2_xdp_snd_pkt_handlerfunction otx2_snd_pkt_handlerfunction otx2_set_rxtstampfunction otx2_skb_add_fragfunction otx2_set_rxhashfunction otx2_free_rcv_segfunction otx2_check_rcv_errorsfunction otx2_rcv_pkt_handlerfunction otx2_rx_napi_handlerfunction otx2_refill_pool_ptrsfunction otx2_zc_submit_pktsfunction otx2_tx_napi_handlerfunction otx2_adjust_adaptive_coalesefunction otx2_napi_handlerfunction otx2_sqe_flushfunction otx2_sqe_add_sgfunction otx2_sqe_add_extfunction otx2_sqe_add_memfunction otx2_sqe_add_hdrfunction otx2_dma_map_tso_skbfunction otx2_tso_frag_dma_addrfunction otx2_sqe_tso_add_sgfunction otx2_sq_append_tsofunction is_hw_tso_supportedfunction otx2_get_sqe_countfunction otx2_validate_network_transportfunction otx2_ptp_is_syncfunction vlanfunction otx2_set_txtstampfunction otx2_sq_append_skbfunction otx2_cleanup_rx_cqesfunction otx2_cleanup_tx_cqesfunction otx2_rxtx_enablefunction otx2_free_pending_sqefunction otx2_xdp_sqe_add_sgfunction otx2_read_free_sqefunction otx2_xdp_sq_append_pktfunction otx2_xdp_rcv_pkt_handlerexport otx2_napi_handlerexport otx2_sq_append_skb
Annotated Snippet
if (timestamp != 1) {
timestamp = pfvf->ptp->convert_tx_ptp_tstmp(timestamp);
err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns);
if (!err) {
memset(&ts, 0, sizeof(ts));
ts.hwtstamp = ns_to_ktime(tsns);
skb_tstamp_tx(skb, &ts);
}
}
}
*tx_bytes += skb->len;
(*tx_pkts)++;
otx2_dma_unmap_skb_frags(pfvf, sg);
napi_consume_skb(skb, budget);
sg->skb = (u64)NULL;
}
static void otx2_set_rxtstamp(struct otx2_nic *pfvf,
struct sk_buff *skb, void *data)
{
u64 timestamp, tsns;
int err;
if (!(pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED))
return;
timestamp = pfvf->ptp->convert_rx_ptp_tstmp(*(u64 *)data);
/* The first 8 bytes is the timestamp */
err = otx2_ptp_tstamp2time(pfvf, timestamp, &tsns);
if (err)
return;
skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(tsns);
}
static bool otx2_skb_add_frag(struct otx2_nic *pfvf, struct sk_buff *skb,
u64 iova, int len, struct nix_rx_parse_s *parse,
int qidx)
{
struct page *page;
int off = 0;
void *va;
va = phys_to_virt(otx2_iova_to_phys(pfvf->iommu_domain, iova));
if (likely(!skb_shinfo(skb)->nr_frags)) {
/* Check if data starts at some nonzero offset
* from the start of the buffer. For now the
* only possible offset is 8 bytes in the case
* where packet is prepended by a timestamp.
*/
if (parse->laptr) {
otx2_set_rxtstamp(pfvf, skb, va);
off = OTX2_HW_TIMESTAMP_LEN;
}
}
page = virt_to_page(va);
if (likely(skb_shinfo(skb)->nr_frags < MAX_SKB_FRAGS)) {
skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
va - page_address(page) + off,
len - off, pfvf->rbsize);
return true;
}
/* If more than MAX_SKB_FRAGS fragments are received then
* give back those buffer pointers to hardware for reuse.
*/
pfvf->hw_ops->aura_freeptr(pfvf, qidx, iova & ~0x07ULL);
return false;
}
static void otx2_set_rxhash(struct otx2_nic *pfvf,
struct nix_cqe_rx_s *cqe, struct sk_buff *skb)
{
enum pkt_hash_types hash_type = PKT_HASH_TYPE_NONE;
struct otx2_rss_info *rss;
u32 hash = 0;
if (!(pfvf->netdev->features & NETIF_F_RXHASH))
return;
rss = &pfvf->hw.rss_info;
if (rss->flowkey_cfg) {
if (rss->flowkey_cfg &
~(NIX_FLOW_KEY_TYPE_IPV4 | NIX_FLOW_KEY_TYPE_IPV6))
hash_type = PKT_HASH_TYPE_L4;
else
Annotation
- Immediate include surface: `linux/etherdevice.h`, `net/ip.h`, `net/tso.h`, `linux/bpf.h`, `linux/bpf_trace.h`, `net/ip6_checksum.h`, `net/xfrm.h`, `net/xdp.h`.
- Detected declarations: `function otx2_get_free_sqe`, `function otx2_sq_set_sqe_base`, `function otx2_nix_cq_op_status`, `function frag_num`, `function otx2_xdp_snd_pkt_handler`, `function otx2_snd_pkt_handler`, `function otx2_set_rxtstamp`, `function otx2_skb_add_frag`, `function otx2_set_rxhash`, `function otx2_free_rcv_seg`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: integration implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.