drivers/net/ethernet/mediatek/mtk_ppe_regs.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/mediatek/mtk_ppe_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/mediatek/mtk_ppe_regs.h
Extension
.h
Size
5623 bytes
Lines
175
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */

#ifndef __MTK_PPE_REGS_H
#define __MTK_PPE_REGS_H

#define MTK_PPE_GLO_CFG				0x200
#define MTK_PPE_GLO_CFG_EN			BIT(0)
#define MTK_PPE_GLO_CFG_TSID_EN			BIT(1)
#define MTK_PPE_GLO_CFG_IP4_L4_CS_DROP		BIT(2)
#define MTK_PPE_GLO_CFG_IP4_CS_DROP		BIT(3)
#define MTK_PPE_GLO_CFG_TTL0_DROP		BIT(4)
#define MTK_PPE_GLO_CFG_PPE_BSWAP		BIT(5)
#define MTK_PPE_GLO_CFG_PSE_HASH_OFS		BIT(6)
#define MTK_PPE_GLO_CFG_MCAST_TB_EN		BIT(7)
#define MTK_PPE_GLO_CFG_FLOW_DROP_KA		BIT(8)
#define MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE	BIT(9)
#define MTK_PPE_GLO_CFG_UDP_LITE_EN		BIT(10)
#define MTK_PPE_GLO_CFG_UDP_LEN_DROP		BIT(11)
#define MTK_PPE_GLO_CFG_MCAST_ENTRIES		GNEMASK(13, 12)
#define MTK_PPE_GLO_CFG_BUSY			BIT(31)

#define MTK_PPE_FLOW_CFG			0x204
#define MTK_PPE_MD_TOAP_BYP_CRSN0		BIT(1)
#define MTK_PPE_MD_TOAP_BYP_CRSN1		BIT(2)
#define MTK_PPE_MD_TOAP_BYP_CRSN2		BIT(3)
#define MTK_PPE_FLOW_CFG_IP4_TCP_FRAG		BIT(6)
#define MTK_PPE_FLOW_CFG_IP4_UDP_FRAG		BIT(7)
#define MTK_PPE_FLOW_CFG_IP6_3T_ROUTE		BIT(8)
#define MTK_PPE_FLOW_CFG_IP6_5T_ROUTE		BIT(9)
#define MTK_PPE_FLOW_CFG_IP6_6RD		BIT(10)
#define MTK_PPE_FLOW_CFG_IP4_NAT		BIT(12)
#define MTK_PPE_FLOW_CFG_IP4_NAPT		BIT(13)
#define MTK_PPE_FLOW_CFG_IP4_DSLITE		BIT(14)
#define MTK_PPE_FLOW_CFG_L2_BRIDGE		BIT(15)
#define MTK_PPE_FLOW_CFG_IP_PROTO_BLACKLIST	BIT(16)
#define MTK_PPE_FLOW_CFG_IP4_NAT_FRAG		BIT(17)
#define MTK_PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL	BIT(18)
#define MTK_PPE_FLOW_CFG_IP4_HASH_GRE_KEY	BIT(19)
#define MTK_PPE_FLOW_CFG_IP6_HASH_GRE_KEY	BIT(20)

#define MTK_PPE_IP_PROTO_CHK			0x208
#define MTK_PPE_IP_PROTO_CHK_IPV4		GENMASK(15, 0)
#define MTK_PPE_IP_PROTO_CHK_IPV6		GENMASK(31, 16)

#define MTK_PPE_TB_CFG				0x21c
#define MTK_PPE_TB_CFG_ENTRY_NUM		GENMASK(2, 0)
#define MTK_PPE_TB_CFG_ENTRY_80B		BIT(3)
#define MTK_PPE_TB_CFG_SEARCH_MISS		GENMASK(5, 4)
#define MTK_PPE_TB_CFG_AGE_PREBIND		BIT(6)
#define MTK_PPE_TB_CFG_AGE_NON_L4		BIT(7)
#define MTK_PPE_TB_CFG_AGE_UNBIND		BIT(8)
#define MTK_PPE_TB_CFG_AGE_TCP			BIT(9)
#define MTK_PPE_TB_CFG_AGE_UDP			BIT(10)
#define MTK_PPE_TB_CFG_AGE_TCP_FIN		BIT(11)
#define MTK_PPE_TB_CFG_KEEPALIVE		GENMASK(13, 12)
#define MTK_PPE_TB_CFG_HASH_MODE		GENMASK(15, 14)
#define MTK_PPE_TB_CFG_SCAN_MODE		GENMASK(17, 16)
#define MTK_PPE_TB_CFG_HASH_DEBUG		GENMASK(19, 18)
#define MTK_PPE_TB_CFG_INFO_SEL			BIT(20)
#define MTK_PPE_TB_TICK_SEL			BIT(24)

#define MTK_PPE_BIND_LMT1			0x230
#define MTK_PPE_NTU_KEEPALIVE			GENMASK(23, 16)

#define MTK_PPE_KEEPALIVE			0x234

enum {
	MTK_PPE_SCAN_MODE_DISABLED,
	MTK_PPE_SCAN_MODE_CHECK_AGE,
	MTK_PPE_SCAN_MODE_KEEPALIVE_AGE,
};

enum {
	MTK_PPE_KEEPALIVE_DISABLE,
	MTK_PPE_KEEPALIVE_UNICAST_CPU,
	MTK_PPE_KEEPALIVE_DUP_CPU = 3,
};

enum {
	MTK_PPE_SEARCH_MISS_ACTION_DROP,
	MTK_PPE_SEARCH_MISS_ACTION_FORWARD = 2,
	MTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD = 3,
};

#define MTK_PPE_TB_BASE				0x220

#define MTK_PPE_TB_USED				0x224
#define MTK_PPE_TB_USED_NUM			GENMASK(13, 0)

Annotation

Implementation Notes