drivers/net/ethernet/mediatek/mtk_wed_wo.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/mediatek/mtk_wed_wo.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/mediatek/mtk_wed_wo.h
Extension
.h
Size
6971 bytes
Lines
284
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct mtk_wed_mcu_hdr {
	/* DW0 */
	u8 version;
	u8 cmd;
	__le16 length;

	/* DW1 */
	__le16 seq;
	__le16 flag;

	/* DW2 */
	__le32 status;

	/* DW3 */
	u8 rsv[20];
};

struct mtk_wed_wo_log_info {
	__le32 sn;
	__le32 total;
	__le32 rro;
	__le32 mod;
};

enum mtk_wed_wo_event {
	MTK_WED_WO_EVT_LOG_DUMP		= 0x1,
	MTK_WED_WO_EVT_PROFILING	= 0x2,
	MTK_WED_WO_EVT_RXCNT_INFO	= 0x3,
};

#define MTK_WED_MODULE_ID_WO		1
#define MTK_FW_DL_TIMEOUT		4000000 /* us */
#define MTK_WOCPU_TIMEOUT		2000000 /* us */

enum {
	MTK_WED_WARP_CMD_FLAG_RSP		= BIT(0),
	MTK_WED_WARP_CMD_FLAG_NEED_RSP		= BIT(1),
	MTK_WED_WARP_CMD_FLAG_FROM_TO_WO	= BIT(2),
};

#define MTK_WED_WO_CPU_MCUSYS_RESET_ADDR	0x15194050
#define MTK_WED_WO_CPU_WO0_MCUSYS_RESET_MASK	0x20
#define MTK_WED_WO_CPU_WO1_MCUSYS_RESET_MASK	0x1

enum {
	MTK_WED_WO_REGION_EMI,
	MTK_WED_WO_REGION_ILM,
	MTK_WED_WO_REGION_DATA,
	MTK_WED_WO_REGION_BOOT,
	__MTK_WED_WO_REGION_MAX,
};

enum mtk_wed_wo_state {
	MTK_WED_WO_STATE_UNDEFINED,
	MTK_WED_WO_STATE_INIT,
	MTK_WED_WO_STATE_ENABLE,
	MTK_WED_WO_STATE_DISABLE,
	MTK_WED_WO_STATE_HALT,
	MTK_WED_WO_STATE_GATING,
	MTK_WED_WO_STATE_SER_RESET,
	MTK_WED_WO_STATE_WF_RESET,
};

enum mtk_wed_wo_done_state {
	MTK_WED_WOIF_UNDEFINED,
	MTK_WED_WOIF_DISABLE_DONE,
	MTK_WED_WOIF_TRIGGER_ENABLE,
	MTK_WED_WOIF_ENABLE_DONE,
	MTK_WED_WOIF_TRIGGER_GATING,
	MTK_WED_WOIF_GATING_DONE,
	MTK_WED_WOIF_TRIGGER_HALT,
	MTK_WED_WOIF_HALT_DONE,
};

enum mtk_wed_dummy_cr_idx {
	MTK_WED_DUMMY_CR_FWDL,
	MTK_WED_DUMMY_CR_WO_STATUS,
};

#define MT7981_FIRMWARE_WO	"mediatek/mt7981_wo.bin"
#define MT7986_FIRMWARE_WO0	"mediatek/mt7986_wo_0.bin"
#define MT7986_FIRMWARE_WO1	"mediatek/mt7986_wo_1.bin"
#define MT7988_FIRMWARE_WO0	"mediatek/mt7988/mt7988_wo_0.bin"
#define MT7988_FIRMWARE_WO1	"mediatek/mt7988/mt7988_wo_1.bin"

#define MTK_WO_MCU_CFG_LS_BASE				0
#define MTK_WO_MCU_CFG_LS_HW_VER_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x000)
#define MTK_WO_MCU_CFG_LS_FW_VER_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x004)
#define MTK_WO_MCU_CFG_LS_CFG_DBG1_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x00c)
#define MTK_WO_MCU_CFG_LS_CFG_DBG2_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x010)

Annotation

Implementation Notes