drivers/net/ethernet/mellanox/mlx5/core/devlink.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/mellanox/mlx5/core/devlink.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/mellanox/mlx5/core/devlink.c- Extension
.c- Size
- 29815 bytes
- Lines
- 1053
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
devlink.hmlx5_core.hfw_reset.hfs_core.heswitch.hesw/qos.hsf/dev/dev.hsf/sf.hlib/nv_param.h
Detected Declarations
function mlx5_devlink_flash_updatefunction mlx5_fw_ver_majorfunction mlx5_fw_ver_minorfunction mlx5_fw_ver_subminorfunction mlx5_devlink_serial_numbers_putfunction mlx5_devlink_info_getfunction mlx5_devlink_reload_fw_activatefunction mlx5_devlink_trigger_fw_live_patchfunction mlx5_devlink_reload_downfunction mlx5_devlink_reload_upfunction mlx5_devlink_trap_initfunction mlx5_devlink_trap_finifunction mlx5_devlink_trap_action_setfunction mlx5_devlink_trap_reportfunction mlx5_devlink_trap_get_num_activefunction mlx5_devlink_traps_get_actionfunction mlx5_devlink_freefunction mlx5_devlink_enable_roce_validatefunction mlx5_devlink_large_group_num_validatefunction mlx5_devlink_eq_depth_validatefunction mlx5_devlink_hairpin_num_queues_validatefunction mlx5_devlink_hairpin_queue_size_validatefunction mlx5_devlink_num_doorbells_validatefunction mlx5_devlink_hairpin_params_init_valuesfunction mlx5_devlink_set_params_init_valuesfunction mlx5_devlink_eth_params_registerfunction mlx5_devlink_eth_params_unregisterfunction mlx5_devlink_pcie_cong_thresh_validatefunction mlx5_devlink_pcie_cong_init_valuesfunction mlx5_devlink_pcie_cong_params_registerfunction mlx5_devlink_pcie_cong_params_unregisterfunction mlx5_devlink_enable_rdma_validatefunction mlx5_devlink_rdma_params_registerfunction mlx5_devlink_rdma_params_unregisterfunction mlx5_devlink_vnet_params_registerfunction mlx5_devlink_vnet_params_unregisterfunction mlx5_devlink_auxdev_params_registerfunction mlx5_devlink_auxdev_params_unregisterfunction mlx5_devlink_max_uc_list_validatefunction mlx5_devlink_max_uc_list_params_registerfunction mlx5_devlink_max_uc_list_params_unregisterfunction mlx5_devlink_traps_registerfunction mlx5_devlink_traps_unregisterfunction mlx5_devlink_params_registerfunction mlx5_devlink_params_unregister
Annotated Snippet
if (!str) {
err = -ENOMEM;
goto end;
}
end = strchrnul(str, ' ');
*end = '\0';
err = devlink_info_board_serial_number_put(req, str);
kfree(str);
if (err)
goto end;
}
start = pci_vpd_find_ro_info_keyword(vpd_data, vpd_size, "V3", &kw_len);
if (start >= 0) {
str = kstrndup(vpd_data + start, kw_len, GFP_KERNEL);
if (!str) {
err = -ENOMEM;
goto end;
}
err = devlink_info_serial_number_put(req, str);
kfree(str);
if (err)
goto end;
}
end:
kfree(vpd_data);
return err;
}
#define DEVLINK_FW_STRING_LEN 32
static int
mlx5_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
struct netlink_ext_ack *extack)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
char version_str[DEVLINK_FW_STRING_LEN];
u32 running_fw, stored_fw;
int err;
if (!mlx5_core_is_pf(dev))
return 0;
err = mlx5_devlink_serial_numbers_put(dev, req, extack);
if (err)
return err;
err = devlink_info_version_fixed_put(req, "fw.psid", dev->board_id);
if (err)
return err;
mlx5_fw_version_query(dev, &running_fw, &stored_fw);
snprintf(version_str, sizeof(version_str), "%d.%d.%04d",
mlx5_fw_ver_major(running_fw), mlx5_fw_ver_minor(running_fw),
mlx5_fw_ver_subminor(running_fw));
err = devlink_info_version_running_put(req, "fw.version", version_str);
if (err)
return err;
err = devlink_info_version_running_put(req,
DEVLINK_INFO_VERSION_GENERIC_FW,
version_str);
if (err)
return err;
/* no pending version, return running (stored) version */
if (stored_fw == 0)
stored_fw = running_fw;
snprintf(version_str, sizeof(version_str), "%d.%d.%04d",
mlx5_fw_ver_major(stored_fw), mlx5_fw_ver_minor(stored_fw),
mlx5_fw_ver_subminor(stored_fw));
err = devlink_info_version_stored_put(req, "fw.version", version_str);
if (err)
return err;
return devlink_info_version_stored_put(req,
DEVLINK_INFO_VERSION_GENERIC_FW,
version_str);
}
static int mlx5_devlink_reload_fw_activate(struct devlink *devlink, struct netlink_ext_ack *extack)
{
struct mlx5_core_dev *dev = devlink_priv(devlink);
u8 reset_level, reset_type, net_port_alive;
int err;
err = mlx5_fw_reset_query(dev, &reset_level, &reset_type);
if (err)
return err;
Annotation
- Immediate include surface: `devlink.h`, `mlx5_core.h`, `fw_reset.h`, `fs_core.h`, `eswitch.h`, `esw/qos.h`, `sf/dev/dev.h`, `sf/sf.h`.
- Detected declarations: `function mlx5_devlink_flash_update`, `function mlx5_fw_ver_major`, `function mlx5_fw_ver_minor`, `function mlx5_fw_ver_subminor`, `function mlx5_devlink_serial_numbers_put`, `function mlx5_devlink_info_get`, `function mlx5_devlink_reload_fw_activate`, `function mlx5_devlink_trigger_fw_live_patch`, `function mlx5_devlink_reload_down`, `function mlx5_devlink_reload_up`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.