drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/mellanox/mlx5/core/en/tc_tun_encap.c- Extension
.c- Size
- 51030 bytes
- Lines
- 1892
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
net/fib_notifier.hnet/nexthop.hnet/ip_tunnels.htc_tun_encap.hfs_core.hen_tc.htc_tun.hrep/tc.hdiag/en_tc_tracepoint.h
Detected Declarations
struct mlx5e_route_keystruct mlx5e_route_entrystruct mlx5e_tc_tun_encapstruct mlx5e_tc_fib_event_datafunction mlx5e_set_int_port_tunnelfunction mlx5e_route_entry_validfunction mlx5e_tc_set_attr_rx_tunfunction mlx5e_tc_flow_all_encaps_validfunction mlx5e_tc_encap_flows_addfunction list_for_each_entryfunction mlx5e_tc_encap_flows_delfunction list_for_each_entryfunction mlx5e_take_tmp_flowfunction mlx5e_take_all_encap_flowsfunction list_for_each_entryfunction mlx5e_take_all_route_decap_flowsfunction mlx5e_get_next_matching_encapfunction mlx5e_encap_validfunction mlx5e_get_next_valid_encapfunction mlx5e_encap_initializedfunction mlx5e_get_next_init_encapfunction mlx5e_tc_update_neigh_used_valuefunction list_for_each_entry_safefunction mlx5e_encap_deallocfunction mlx5e_decap_deallocfunction mlx5e_encap_putfunction mlx5e_encap_put_lockedfunction mlx5e_decap_putfunction mlx5e_detach_encapfunction mlx5e_detach_decapfunction mlx5e_tc_tun_encap_info_equal_genericfunction mlx5e_tc_tun_encap_info_equal_optionsfunction cmp_decap_infofunction hash_encap_infofunction hash_decap_infofunction mlx5e_encap_takefunction mlx5e_decap_takefunction mlx5e_encap_getfunction hash_for_each_possible_rcufunction mlx5e_decap_getfunction hash_for_each_possible_rcufunction is_duplicated_encap_entryfunction mlx5e_set_vf_tunnelfunction mlx5e_update_vf_tunnelfunction mlx5e_route_tbl_get_last_updatefunction mlx5e_attach_encapfunction mlx5e_attach_decapfunction mlx5e_tc_tun_encap_dests_set
Annotated Snippet
struct mlx5e_route_key {
int ip_version;
union {
__be32 v4;
struct in6_addr v6;
} endpoint_ip;
};
struct mlx5e_route_entry {
struct mlx5e_route_key key;
struct list_head encap_entries;
struct list_head decap_flows;
u32 flags;
struct hlist_node hlist;
refcount_t refcnt;
int tunnel_dev_index;
struct rcu_head rcu;
};
struct mlx5e_tc_tun_encap {
struct mlx5e_priv *priv;
struct notifier_block fib_nb;
spinlock_t route_lock; /* protects route_tbl */
unsigned long route_tbl_last_update;
DECLARE_HASHTABLE(route_tbl, 8);
};
static bool mlx5e_route_entry_valid(struct mlx5e_route_entry *r)
{
return r->flags & MLX5E_ROUTE_ENTRY_VALID;
}
int mlx5e_tc_set_attr_rx_tun(struct mlx5e_tc_flow *flow,
struct mlx5_flow_spec *spec)
{
struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
struct mlx5_rx_tun_attr *tun_attr;
void *daddr, *saddr;
u8 ip_version;
tun_attr = kvzalloc_obj(*tun_attr);
if (!tun_attr)
return -ENOMEM;
esw_attr->rx_tun_attr = tun_attr;
ip_version = mlx5e_tc_get_ip_version(spec, true);
if (ip_version == 4) {
daddr = MLX5_ADDR_OF(fte_match_param, spec->match_value,
outer_headers.dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
saddr = MLX5_ADDR_OF(fte_match_param, spec->match_value,
outer_headers.src_ipv4_src_ipv6.ipv4_layout.ipv4);
tun_attr->dst_ip.v4 = *(__be32 *)daddr;
tun_attr->src_ip.v4 = *(__be32 *)saddr;
if (!tun_attr->dst_ip.v4 || !tun_attr->src_ip.v4)
return 0;
}
#if IS_ENABLED(CONFIG_INET) && IS_ENABLED(CONFIG_IPV6)
else if (ip_version == 6) {
int ipv6_size = MLX5_FLD_SZ_BYTES(ipv6_layout, ipv6);
daddr = MLX5_ADDR_OF(fte_match_param, spec->match_value,
outer_headers.dst_ipv4_dst_ipv6.ipv6_layout.ipv6);
saddr = MLX5_ADDR_OF(fte_match_param, spec->match_value,
outer_headers.src_ipv4_src_ipv6.ipv6_layout.ipv6);
memcpy(&tun_attr->dst_ip.v6, daddr, ipv6_size);
memcpy(&tun_attr->src_ip.v6, saddr, ipv6_size);
if (ipv6_addr_any(&tun_attr->dst_ip.v6) ||
ipv6_addr_any(&tun_attr->src_ip.v6))
return 0;
}
#endif
/* Only set the flag if both src and dst ip addresses exist. They are
* required to establish routing.
*/
flow_flag_set(flow, TUN_RX);
flow->attr->tun_ip_version = ip_version;
return 0;
}
static bool mlx5e_tc_flow_all_encaps_valid(struct mlx5_esw_flow_attr *esw_attr)
{
bool all_flow_encaps_valid = true;
int i;
/* Flow can be associated with multiple encap entries.
* Before offloading the flow verify that all of them have
* a valid neighbour.
*/
for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
Annotation
- Immediate include surface: `net/fib_notifier.h`, `net/nexthop.h`, `net/ip_tunnels.h`, `tc_tun_encap.h`, `fs_core.h`, `en_tc.h`, `tc_tun.h`, `rep/tc.h`.
- Detected declarations: `struct mlx5e_route_key`, `struct mlx5e_route_entry`, `struct mlx5e_tc_tun_encap`, `struct mlx5e_tc_fib_event_data`, `function mlx5e_set_int_port_tunnel`, `function mlx5e_route_entry_valid`, `function mlx5e_tc_set_attr_rx_tun`, `function mlx5e_tc_flow_all_encaps_valid`, `function mlx5e_tc_encap_flows_add`, `function list_for_each_entry`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.