drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h- Extension
.h- Size
- 3508 bytes
- Lines
- 112
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/mlx5/eq.hmlx5_core.hlib/eq.hfpga/cmd.h
Detected Declarations
struct mlx5_fpga_devicefunction mlx5_fpga_initfunction mlx5_fpga_cleanupfunction mlx5_fpga_device_stop
Annotated Snippet
struct mlx5_fpga_device {
struct mlx5_core_dev *mdev;
struct mlx5_nb fpga_err_nb;
struct mlx5_nb fpga_qp_err_nb;
spinlock_t state_lock; /* Protects state transitions */
enum mlx5_fpga_status state;
enum mlx5_fpga_image last_admin_image;
enum mlx5_fpga_image last_oper_image;
/* QP Connection resources */
struct {
u32 pdn;
u32 mkey;
struct mlx5_uars_page *uar;
} conn_res;
};
#define mlx5_fpga_dbg(__adev, format, ...) \
mlx5_core_dbg((__adev)->mdev, "FPGA: %s:%d:(pid %d): " format, \
__func__, __LINE__, current->pid, ##__VA_ARGS__)
#define mlx5_fpga_err(__adev, format, ...) \
mlx5_core_err((__adev)->mdev, "FPGA: %s:%d:(pid %d): " format, \
__func__, __LINE__, current->pid, ##__VA_ARGS__)
#define mlx5_fpga_warn(__adev, format, ...) \
mlx5_core_warn((__adev)->mdev, "FPGA: %s:%d:(pid %d): " format, \
__func__, __LINE__, current->pid, ##__VA_ARGS__)
#define mlx5_fpga_warn_ratelimited(__adev, format, ...) \
mlx5_core_err_rl((__adev)->mdev, "FPGA: %s:%d: " \
format, __func__, __LINE__, ##__VA_ARGS__)
#define mlx5_fpga_notice(__adev, format, ...) \
mlx5_core_info((__adev)->mdev, "FPGA: " format, ##__VA_ARGS__)
#define mlx5_fpga_info(__adev, format, ...) \
mlx5_core_info((__adev)->mdev, "FPGA: " format, ##__VA_ARGS__)
int mlx5_fpga_init(struct mlx5_core_dev *mdev);
void mlx5_fpga_cleanup(struct mlx5_core_dev *mdev);
int mlx5_fpga_device_start(struct mlx5_core_dev *mdev);
void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev);
#else
static inline int mlx5_fpga_init(struct mlx5_core_dev *mdev)
{
return 0;
}
static inline void mlx5_fpga_cleanup(struct mlx5_core_dev *mdev)
{
}
static inline int mlx5_fpga_device_start(struct mlx5_core_dev *mdev)
{
return 0;
}
static inline void mlx5_fpga_device_stop(struct mlx5_core_dev *mdev)
{
}
#endif
#endif /* __MLX5_FPGA_CORE_H__ */
Annotation
- Immediate include surface: `linux/mlx5/eq.h`, `mlx5_core.h`, `lib/eq.h`, `fpga/cmd.h`.
- Detected declarations: `struct mlx5_fpga_device`, `function mlx5_fpga_init`, `function mlx5_fpga_cleanup`, `function mlx5_fpga_device_stop`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.