drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c- Extension
.c- Size
- 44530 bytes
- Lines
- 1655
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/clocksource.hlinux/highmem.hlinux/log2.hlinux/ptp_clock_kernel.hrdma/mlx5-abi.hlib/eq.hen.hclock.hlinux/timekeeping.hlinux/cpufeature.h
Detected Declarations
struct mlx5_clock_dev_statestruct mlx5_clock_privfunction mlx5_clock_lockdep_assertfunction mlx5_clock_lockfunction mlx5_clock_unlockfunction mlx5_real_time_modefunction mlx5_npps_real_time_supportedfunction mlx5_modify_mtutc_allowedfunction mlx5_clock_identity_getfunction mlx5_ptp_shift_constantfunction mlx5_clock_getmaxphasefunction mlx5_ptp_getmaxphasefunction mlx5_is_mtutc_time_adj_capfunction mlx5_set_mtutcfunction mlx5_is_ptm_source_time_availablefunction mlx5_mtctr_readfunction mlx5_mtctr_syncdevicetimefunction mlx5_mtctr_syncdevicecyclestimefunction mlx5_ptp_getcrosststampfunction mlx5_ptp_getcrosscyclesfunction mlx5_read_timefunction read_internal_timerfunction mlx5_update_clock_info_pagefunction mlx5_pps_outfunction mlx5_timestamp_overflowfunction mlx5_ptp_settime_real_timefunction mlx5_clock_settimefunction mlx5_ptp_settimefunction mlx5_ptp_gettimex_real_timefunction mlx5_ptp_gettimexfunction mlx5_ptp_getcyclesxfunction mlx5_ptp_adjtime_real_timefunction mlx5_ptp_adjtimefunction mlx5_ptp_adjphasefunction mlx5_ptp_freq_adj_real_timefunction mlx5_ptp_adjfinefunction mlx5_extts_configurefunction find_target_cyclesfunction perout_conf_internal_timerfunction perout_conf_real_timefunction perout_conf_1ppsfunction mlx5_perout_conf_out_pulse_durationfunction perout_conf_npps_real_timefunction mlx5_perout_configurefunction mlx5_pps_configurefunction mlx5_ptp_enablefunction mlx5_ptp_verifyfunction mlx5_query_mtpps_pin_mode
Annotated Snippet
struct mlx5_clock_dev_state {
struct mlx5_core_dev *mdev;
struct mlx5_devcom_comp_dev *compdev;
struct mlx5_nb pps_nb;
struct work_struct out_work;
};
struct mlx5_clock_priv {
struct mlx5_clock clock;
struct mlx5_core_dev *mdev;
struct mutex lock; /* protect mdev and used in PTP callbacks */
struct mlx5_core_dev *event_mdev;
};
static struct mlx5_clock_priv *clock_priv(struct mlx5_clock *clock)
{
return container_of(clock, struct mlx5_clock_priv, clock);
}
static void mlx5_clock_lockdep_assert(struct mlx5_clock *clock)
{
if (!clock->shared)
return;
lockdep_assert(lockdep_is_held(&clock_priv(clock)->lock));
}
static struct mlx5_core_dev *mlx5_clock_mdev_get(struct mlx5_clock *clock)
{
mlx5_clock_lockdep_assert(clock);
return clock_priv(clock)->mdev;
}
static void mlx5_clock_lock(struct mlx5_clock *clock)
{
if (!clock->shared)
return;
mutex_lock(&clock_priv(clock)->lock);
}
static void mlx5_clock_unlock(struct mlx5_clock *clock)
{
if (!clock->shared)
return;
mutex_unlock(&clock_priv(clock)->lock);
}
static bool mlx5_real_time_mode(struct mlx5_core_dev *mdev)
{
return (mlx5_is_real_time_rq(mdev) || mlx5_is_real_time_sq(mdev));
}
static bool mlx5_npps_real_time_supported(struct mlx5_core_dev *mdev)
{
return (mlx5_real_time_mode(mdev) &&
MLX5_CAP_MCAM_FEATURE(mdev, npps_period) &&
MLX5_CAP_MCAM_FEATURE(mdev, out_pulse_duration_ns));
}
static bool mlx5_modify_mtutc_allowed(struct mlx5_core_dev *mdev)
{
return MLX5_CAP_MCAM_FEATURE(mdev, ptpcyc2realtime_modify);
}
static int mlx5_clock_identity_get(struct mlx5_core_dev *mdev,
u8 identify[MLX5_RT_CLOCK_IDENTITY_SIZE])
{
u32 out[MLX5_ST_SZ_DW(mrtcq_reg)] = {};
u32 in[MLX5_ST_SZ_DW(mrtcq_reg)] = {};
int err;
err = mlx5_core_access_reg(mdev, in, sizeof(in),
out, sizeof(out), MLX5_REG_MRTCQ, 0, 0);
if (!err)
memcpy(identify, MLX5_ADDR_OF(mrtcq_reg, out, rt_clock_identity),
MLX5_RT_CLOCK_IDENTITY_SIZE);
return err;
}
static u32 mlx5_ptp_shift_constant(u32 dev_freq_khz)
{
/* Optimal shift constant leads to corrections above just 1 scaled ppm.
*
* Two sets of equations are needed to derive the optimal shift
* constant for the cyclecounter.
*
Annotation
- Immediate include surface: `linux/clocksource.h`, `linux/highmem.h`, `linux/log2.h`, `linux/ptp_clock_kernel.h`, `rdma/mlx5-abi.h`, `lib/eq.h`, `en.h`, `clock.h`.
- Detected declarations: `struct mlx5_clock_dev_state`, `struct mlx5_clock_priv`, `function mlx5_clock_lockdep_assert`, `function mlx5_clock_lock`, `function mlx5_clock_unlock`, `function mlx5_real_time_mode`, `function mlx5_npps_real_time_supported`, `function mlx5_modify_mtutc_allowed`, `function mlx5_clock_identity_get`, `function mlx5_ptp_shift_constant`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.