drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c

File Facts

System

Linux kernel

Corpus path

drivers/net/ethernet/mellanox/mlx5/core/lib/nv_param.c

Extension

.c

Size

22692 bytes

Lines

800

Domain

Driver Families

Bucket

drivers/net

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• nv_param.h
• mlx5_core.h

Detected Declarations

• struct mlx5_ifc_configuration_item_type_class_global_bits
• struct mlx5_ifc_configuration_item_type_class_per_host_pf_bits
• struct mlx5_ifc_config_item_bits
• struct mlx5_ifc_mnvda_reg_bits
• struct mlx5_ifc_nv_global_pci_conf_bits
• struct mlx5_ifc_nv_global_pci_cap_bits
• struct mlx5_ifc_nv_pf_pci_conf_bits
• struct mlx5_ifc_nv_sw_offload_conf_bits
• struct mlx5_ifc_nv_sw_offload_cap_bits
• struct mlx5_ifc_nv_sw_accelerate_conf_bits
• enum swp_l4_csum_mode
• function MLX5_BYTE_OFF
• function mlx5_nv_param_write
• function mlx5_nv_param_read_sw_offload_conf
• function mlx5_nv_param_read_sw_offload_cap
• function mlx5_nv_param_read_sw_accelerate_conf
• function mlx5_nv_param_devlink_cqe_compress_get
• function mlx5_nv_param_devlink_cqe_compress_validate
• function mlx5_nv_param_devlink_cqe_compress_set
• function mlx5_swp_l4_csum_mode_get
• function mlx5_devlink_swp_l4_csum_mode_get
• function mlx5_devlink_swp_l4_csum_mode_validate
• function mlx5_swp_l4_csum_mode_set
• function mlx5_devlink_swp_l4_csum_mode_set
• function mlx5_devlink_swp_l4_csum_mode_get_default
• function mlx5_devlink_swp_l4_csum_mode_set_default
• function mlx5_nv_param_read_global_pci_conf
• function mlx5_nv_param_read_global_pci_cap
• function mlx5_nv_param_read_per_host_pf_conf
• function mlx5_devlink_enable_sriov_get
• function mlx5_devlink_enable_sriov_set
• function mlx5_devlink_total_vfs_get
• function mlx5_devlink_total_vfs_set
• function mlx5_devlink_total_vfs_validate
• function mlx5_nv_param_register_dl_params
• function mlx5_nv_param_unregister_dl_params

Annotated Snippet

struct mlx5_ifc_configuration_item_type_class_global_bits {
	u8         type_class[0x8];
	u8         parameter_index[0x18];
};

struct mlx5_ifc_configuration_item_type_class_per_host_pf_bits {
	u8         type_class[0x8];
	u8         pf_index[0x6];
	u8         pci_bus_index[0x8];
	u8         parameter_index[0xa];
};

union mlx5_ifc_config_item_type_auto_bits {
	struct mlx5_ifc_configuration_item_type_class_global_bits
				configuration_item_type_class_global;
	struct mlx5_ifc_configuration_item_type_class_per_host_pf_bits
				configuration_item_type_class_per_host_pf;
	u8 reserved_at_0[0x20];
};

enum {
	MLX5_ACCESS_MODE_NEXT = 0,
	MLX5_ACCESS_MODE_CURRENT,
	MLX5_ACCESS_MODE_DEFAULT,
};

struct mlx5_ifc_config_item_bits {
	u8         valid[0x2];
	u8         priority[0x2];
	u8         header_type[0x2];
	u8         ovr_en[0x1];
	u8         rd_en[0x1];
	u8         access_mode[0x2];
	u8         reserved_at_a[0x1];
	u8         writer_id[0x5];
	u8         version[0x4];
	u8         reserved_at_14[0x2];
	u8         host_id_valid[0x1];
	u8         length[0x9];

	union mlx5_ifc_config_item_type_auto_bits type;

	u8         reserved_at_40[0x10];
	u8         crc16[0x10];
};

struct mlx5_ifc_mnvda_reg_bits {
	struct mlx5_ifc_config_item_bits configuration_item_header;

	u8         configuration_item_data[64][0x20];
};

struct mlx5_ifc_nv_global_pci_conf_bits {
	u8         sriov_valid[0x1];
	u8         reserved_at_1[0x10];
	u8         per_pf_total_vf[0x1];
	u8         reserved_at_12[0xe];

	u8         sriov_en[0x1];
	u8         reserved_at_21[0xf];
	u8         total_vfs[0x10];

	u8         reserved_at_40[0x20];
};

struct mlx5_ifc_nv_global_pci_cap_bits {
	u8         max_vfs_per_pf_valid[0x1];
	u8         reserved_at_1[0x13];
	u8         per_pf_total_vf_supported[0x1];
	u8         reserved_at_15[0xb];

	u8         sriov_support[0x1];
	u8         reserved_at_21[0xf];
	u8         max_vfs_per_pf[0x10];

	u8         reserved_at_40[0x60];
};

struct mlx5_ifc_nv_pf_pci_conf_bits {
	u8         reserved_at_0[0x9];
	u8         pf_total_vf_en[0x1];
	u8         reserved_at_a[0x16];

	u8         reserved_at_20[0x20];

	u8         reserved_at_40[0x10];
	u8         total_vf[0x10];

	u8         reserved_at_60[0x20];
};

Annotation

• Immediate include surface: `nv_param.h`, `mlx5_core.h`.
• Detected declarations: `struct mlx5_ifc_configuration_item_type_class_global_bits`, `struct mlx5_ifc_configuration_item_type_class_per_host_pf_bits`, `struct mlx5_ifc_config_item_bits`, `struct mlx5_ifc_mnvda_reg_bits`, `struct mlx5_ifc_nv_global_pci_conf_bits`, `struct mlx5_ifc_nv_global_pci_cap_bits`, `struct mlx5_ifc_nv_pf_pci_conf_bits`, `struct mlx5_ifc_nv_sw_offload_conf_bits`, `struct mlx5_ifc_nv_sw_offload_cap_bits`, `struct mlx5_ifc_nv_sw_accelerate_conf_bits`.
• Atlas domain: Driver Families / drivers/net.
• Implementation status: source implementation candidate.
• Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.