drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c- Extension
.c- Size
- 21467 bytes
- Lines
- 821
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/pci.hlinux/interrupt.hlinux/notifier.hlinux/mlx5/driver.hlinux/mlx5/vport.hmlx5_core.hmlx5_irq.hpci_irq.hlib/sf.hlib/eq.hlinux/cpu_rmap.h
Detected Declarations
struct mlx5_irqstruct mlx5_irq_tablefunction mlx5_core_func_to_vportfunction mlx5_get_default_msix_vec_countfunction mlx5_set_msix_vec_countfunction mlx5_irq_table_free_irqsfunction irq_releasefunction mlx5_irq_putfunction mlx5_irq_read_lockedfunction mlx5_irq_get_lockedfunction irq_getfunction irq_int_handlerfunction irq_sf_set_namefunction irq_set_namefunction mlx5_irq_attach_nbfunction mlx5_irq_detach_nbfunction mlx5_irq_get_irqfunction mlx5_irq_get_indexfunction irq_pool_request_vectorfunction sf_comp_irq_pool_getfunction mlx5_irq_table_get_comp_irq_poolfunction _mlx5_irq_releasefunction mlx5_ctrl_irq_releasefunction mlx5_irq_release_vectorfunction irq_pool_allocfunction irq_pool_freefunction irq_pools_initfunction irq_pools_destroyfunction mlx5_irq_pool_free_irqsfunction mlx5_irq_pools_free_irqsfunction mlx5_irq_table_initfunction mlx5_irq_table_cleanupfunction mlx5_irq_table_get_num_compfunction mlx5_irq_table_createfunction mlx5_irq_table_destroyfunction mlx5_irq_table_free_irqsfunction mlx5_irq_table_get_sfs_vec
Annotated Snippet
struct mlx5_irq {
struct atomic_notifier_head nh;
cpumask_var_t mask;
char name[MLX5_MAX_IRQ_FORMATTED_NAME];
struct mlx5_irq_pool *pool;
int refcount;
struct msi_map map;
u32 pool_index;
};
struct mlx5_irq_table {
struct mlx5_irq_pool *pcif_pool;
struct mlx5_irq_pool *sf_ctrl_pool;
struct mlx5_irq_pool *sf_comp_pool;
};
static int mlx5_core_func_to_vport(const struct mlx5_core_dev *dev,
int func,
bool ec_vf_func)
{
if (!ec_vf_func)
return func;
return mlx5_core_ec_vf_vport_base(dev) + func - 1;
}
/**
* mlx5_get_default_msix_vec_count - Get the default number of MSI-X vectors
* to be assigned to each VF.
* @dev: PF to work on
* @num_vfs: Number of enabled VFs
*/
int mlx5_get_default_msix_vec_count(struct mlx5_core_dev *dev, int num_vfs)
{
int num_vf_msix, min_msix, max_msix;
num_vf_msix = MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix);
if (!num_vf_msix)
return 0;
min_msix = MLX5_CAP_GEN(dev, min_dynamic_vf_msix_table_size);
max_msix = MLX5_CAP_GEN(dev, max_dynamic_vf_msix_table_size);
/* Limit maximum number of MSI-X vectors so the default configuration
* has some available in the pool. This will allow the user to increase
* the number of vectors in a VF without having to first size-down other
* VFs.
*/
return max(min(num_vf_msix / num_vfs, max_msix / 2), min_msix);
}
/**
* mlx5_set_msix_vec_count - Set dynamically allocated MSI-X on the VF
* @dev: PF to work on
* @function_id: Internal PCI VF function IDd
* @msix_vec_count: Number of MSI-X vectors to set
*/
int mlx5_set_msix_vec_count(struct mlx5_core_dev *dev, int function_id,
int msix_vec_count)
{
int query_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
int num_vf_msix, min_msix, max_msix;
void *query_cap, *hca_caps;
bool ec_vf_function;
int vport;
int ret;
num_vf_msix = MLX5_CAP_GEN_MAX(dev, num_total_dynamic_vf_msix);
if (!num_vf_msix)
return 0;
if (!MLX5_CAP_GEN(dev, vport_group_manager) || !mlx5_core_is_pf(dev))
return -EOPNOTSUPP;
min_msix = MLX5_CAP_GEN(dev, min_dynamic_vf_msix_table_size);
max_msix = MLX5_CAP_GEN(dev, max_dynamic_vf_msix_table_size);
if (msix_vec_count < min_msix)
return -EINVAL;
if (msix_vec_count > max_msix)
return -EOVERFLOW;
query_cap = kvzalloc(query_sz, GFP_KERNEL);
if (!query_cap)
return -ENOMEM;
ec_vf_function = mlx5_core_ec_sriov_enabled(dev);
vport = mlx5_core_func_to_vport(dev, function_id, ec_vf_function);
ret = mlx5_vport_get_other_func_general_cap(dev, vport, query_cap);
if (ret)
Annotation
- Immediate include surface: `linux/pci.h`, `linux/interrupt.h`, `linux/notifier.h`, `linux/mlx5/driver.h`, `linux/mlx5/vport.h`, `mlx5_core.h`, `mlx5_irq.h`, `pci_irq.h`.
- Detected declarations: `struct mlx5_irq`, `struct mlx5_irq_table`, `function mlx5_core_func_to_vport`, `function mlx5_get_default_msix_vec_count`, `function mlx5_set_msix_vec_count`, `function mlx5_irq_table_free_irqs`, `function irq_release`, `function mlx5_irq_put`, `function mlx5_irq_read_locked`, `function mlx5_irq_get_locked`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.