drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/definer.h- Extension
.h- Size
- 22272 bytes
- Lines
- 832
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct mlx5hws_definer_fcstruct mlx5_ifc_definer_hl_eth_l2_bitsstruct mlx5_ifc_definer_hl_eth_l2_src_bitsstruct mlx5_ifc_definer_hl_ib_l2_bitsstruct mlx5_ifc_definer_hl_eth_l3_bitsstruct mlx5_ifc_definer_hl_eth_l4_bitsstruct mlx5_ifc_definer_hl_src_qp_gvmi_bitsstruct mlx5_ifc_definer_hl_ib_l4_bitsstruct mlx5_ifc_definer_hl_oks1_bitsstruct mlx5_ifc_definer_hl_oks2_bitsstruct mlx5_ifc_definer_hl_voq_bitsstruct mlx5_ifc_definer_hl_ipv4_src_dst_bitsstruct mlx5_ifc_definer_hl_random_number_bitsstruct mlx5_ifc_definer_hl_ipv6_addr_bitsstruct mlx5_ifc_definer_tcp_icmp_header_bitsstruct mlx5_ifc_definer_hl_tunnel_header_bitsstruct mlx5_ifc_definer_hl_ipsec_bitsstruct mlx5_ifc_definer_hl_metadata_bitsstruct mlx5_ifc_definer_hl_flex_parser_bitsstruct mlx5_ifc_definer_hl_registers_bitsstruct mlx5_ifc_definer_hl_mpls_bitsstruct mlx5_ifc_definer_hl_bitsstruct mlx5_ifc_header_gtp_bitsstruct mlx5_ifc_header_opt_gtp_bitsstruct mlx5_ifc_header_gtp_psc_bitsstruct mlx5_ifc_header_ipv6_vtc_bitsstruct mlx5_ifc_header_ipv6_routing_ext_bitsstruct mlx5_ifc_header_vxlan_bitsstruct mlx5_ifc_header_vxlan_gpe_bitsstruct mlx5_ifc_header_gre_bitsstruct mlx5_ifc_header_geneve_bitsstruct mlx5_ifc_header_geneve_opt_bitsstruct mlx5_ifc_header_icmp_bitsstruct mlx5hws_definerstruct mlx5hws_definer_cachestruct mlx5hws_definer_cache_itemenum mlx5hws_definer_fnameenum mlx5hws_definer_match_criteriaenum mlx5hws_definer_typeenum mlx5hws_definer_match_flagenum mlx5hws_integrity_ok1_bitsenum mlx5hws_definer_gtpfunction mlx5hws_definer_is_jumbo
Annotated Snippet
struct mlx5hws_definer_fc {
struct mlx5hws_context *ctx;
/* Source */
u32 s_byte_off;
int s_bit_off;
u32 s_bit_mask;
/* Destination */
u32 byte_off;
int bit_off;
u32 bit_mask;
enum mlx5hws_definer_fname fname;
void (*tag_set)(struct mlx5hws_definer_fc *fc,
void *mach_param,
u8 *tag);
void (*tag_mask_set)(struct mlx5hws_definer_fc *fc,
void *mach_param,
u8 *tag);
};
struct mlx5_ifc_definer_hl_eth_l2_bits {
u8 dmac_47_16[0x20];
u8 dmac_15_0[0x10];
u8 l3_ethertype[0x10];
u8 reserved_at_40[0x1];
u8 sx_sniffer[0x1];
u8 functional_lb[0x1];
u8 ip_fragmented[0x1];
u8 qp_type[0x2];
u8 encap_type[0x2];
u8 port_number[0x2];
u8 l3_type[0x2];
u8 l4_type_bwc[0x2];
u8 first_vlan_qualifier[0x2];
u8 first_priority[0x3];
u8 first_cfi[0x1];
u8 first_vlan_id[0xc];
u8 l4_type[0x4];
u8 reserved_at_64[0x2];
u8 ipsec_layer[0x2];
u8 l2_type[0x2];
u8 force_lb[0x1];
u8 l2_ok[0x1];
u8 l3_ok[0x1];
u8 l4_ok[0x1];
u8 second_vlan_qualifier[0x2];
u8 second_priority[0x3];
u8 second_cfi[0x1];
u8 second_vlan_id[0xc];
};
struct mlx5_ifc_definer_hl_eth_l2_src_bits {
u8 smac_47_16[0x20];
u8 smac_15_0[0x10];
u8 loopback_syndrome[0x8];
u8 l3_type[0x2];
u8 l4_type_bwc[0x2];
u8 first_vlan_qualifier[0x2];
u8 ip_fragmented[0x1];
u8 functional_lb[0x1];
};
struct mlx5_ifc_definer_hl_ib_l2_bits {
u8 sx_sniffer[0x1];
u8 force_lb[0x1];
u8 functional_lb[0x1];
u8 reserved_at_3[0x3];
u8 port_number[0x2];
u8 sl[0x4];
u8 qp_type[0x2];
u8 lnh[0x2];
u8 dlid[0x10];
u8 vl[0x4];
u8 lrh_packet_length[0xc];
u8 slid[0x10];
};
struct mlx5_ifc_definer_hl_eth_l3_bits {
u8 ip_version[0x4];
u8 ihl[0x4];
union {
u8 tos[0x8];
struct {
u8 dscp[0x6];
u8 ecn[0x2];
};
};
u8 time_to_live_hop_limit[0x8];
u8 protocol_next_header[0x8];
u8 identification[0x10];
union {
Annotation
- Detected declarations: `struct mlx5hws_definer_fc`, `struct mlx5_ifc_definer_hl_eth_l2_bits`, `struct mlx5_ifc_definer_hl_eth_l2_src_bits`, `struct mlx5_ifc_definer_hl_ib_l2_bits`, `struct mlx5_ifc_definer_hl_eth_l3_bits`, `struct mlx5_ifc_definer_hl_eth_l4_bits`, `struct mlx5_ifc_definer_hl_src_qp_gvmi_bits`, `struct mlx5_ifc_definer_hl_ib_l4_bits`, `struct mlx5_ifc_definer_hl_oks1_bits`, `struct mlx5_ifc_definer_hl_oks2_bits`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.