drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste_v3.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste_v3.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste_v3.c- Extension
.c- Size
- 10791 bytes
- Lines
- 264
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
dr_ste_v1.hdr_ste_v2.h
Detected Declarations
function dr_ste_v3_set_encapfunction dr_ste_v3_set_push_vlanfunction dr_ste_v3_set_pop_vlanfunction dr_ste_v3_set_encap_l3function dr_ste_v3_set_rx_decapfunction dr_ste_v3_set_insert_hdrfunction dr_ste_v3_set_remove_hdrfunction dr_ste_v3_set_action_decap_l3_list
Annotated Snippet
// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
/* Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
#include "dr_ste_v1.h"
#include "dr_ste_v2.h"
static void dr_ste_v3_set_encap(u8 *hw_ste_p, u8 *d_action,
u32 reformat_id, int size)
{
MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action, action_id,
DR_STE_V1_ACTION_ID_INSERT_POINTER);
/* The hardware expects here size in words (2 byte) */
MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action, size, size / 2);
MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action, pointer, reformat_id);
MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action, attributes,
DR_STE_V1_ACTION_INSERT_PTR_ATTR_ENCAP);
dr_ste_v1_set_reparse(hw_ste_p);
}
static void dr_ste_v3_set_push_vlan(u8 *ste, u8 *d_action,
u32 vlan_hdr)
{
MLX5_SET(ste_double_action_insert_with_inline_v3, d_action, action_id,
DR_STE_V1_ACTION_ID_INSERT_INLINE);
/* The hardware expects here offset to vlan header in words (2 byte) */
MLX5_SET(ste_double_action_insert_with_inline_v3, d_action, start_offset,
HDR_LEN_L2_MACS >> 1);
MLX5_SET(ste_double_action_insert_with_inline_v3, d_action, inline_data, vlan_hdr);
dr_ste_v1_set_reparse(ste);
}
static void dr_ste_v3_set_pop_vlan(u8 *hw_ste_p, u8 *s_action,
u8 vlans_num)
{
MLX5_SET(ste_single_action_remove_header_size_v3, s_action,
action_id, DR_STE_V1_ACTION_ID_REMOVE_BY_SIZE);
MLX5_SET(ste_single_action_remove_header_size_v3, s_action,
start_anchor, DR_STE_HEADER_ANCHOR_1ST_VLAN);
/* The hardware expects here size in words (2 byte) */
MLX5_SET(ste_single_action_remove_header_size_v3, s_action,
remove_size, (HDR_LEN_L2_VLAN >> 1) * vlans_num);
dr_ste_v1_set_reparse(hw_ste_p);
}
static void dr_ste_v3_set_encap_l3(u8 *hw_ste_p,
u8 *frst_s_action,
u8 *scnd_d_action,
u32 reformat_id,
int size)
{
/* Remove L2 headers */
MLX5_SET(ste_single_action_remove_header_v3, frst_s_action, action_id,
DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER);
MLX5_SET(ste_single_action_remove_header_v3, frst_s_action, end_anchor,
DR_STE_HEADER_ANCHOR_IPV6_IPV4);
/* Encapsulate with given reformat ID */
MLX5_SET(ste_double_action_insert_with_ptr_v3, scnd_d_action, action_id,
DR_STE_V1_ACTION_ID_INSERT_POINTER);
/* The hardware expects here size in words (2 byte) */
MLX5_SET(ste_double_action_insert_with_ptr_v3, scnd_d_action, size, size / 2);
MLX5_SET(ste_double_action_insert_with_ptr_v3, scnd_d_action, pointer, reformat_id);
MLX5_SET(ste_double_action_insert_with_ptr_v3, scnd_d_action, attributes,
DR_STE_V1_ACTION_INSERT_PTR_ATTR_ENCAP);
dr_ste_v1_set_reparse(hw_ste_p);
}
static void dr_ste_v3_set_rx_decap(u8 *hw_ste_p, u8 *s_action)
{
MLX5_SET(ste_single_action_remove_header_v3, s_action, action_id,
DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER);
MLX5_SET(ste_single_action_remove_header_v3, s_action, decap, 1);
MLX5_SET(ste_single_action_remove_header_v3, s_action, vni_to_cqe, 1);
MLX5_SET(ste_single_action_remove_header_v3, s_action, end_anchor,
DR_STE_HEADER_ANCHOR_INNER_MAC);
dr_ste_v1_set_reparse(hw_ste_p);
}
static void dr_ste_v3_set_insert_hdr(u8 *hw_ste_p, u8 *d_action,
u32 reformat_id, u8 anchor,
u8 offset, int size)
{
MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action,
action_id, DR_STE_V1_ACTION_ID_INSERT_POINTER);
MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action,
start_anchor, anchor);
Annotation
- Immediate include surface: `dr_ste_v1.h`, `dr_ste_v2.h`.
- Detected declarations: `function dr_ste_v3_set_encap`, `function dr_ste_v3_set_push_vlan`, `function dr_ste_v3_set_pop_vlan`, `function dr_ste_v3_set_encap_l3`, `function dr_ste_v3_set_rx_decap`, `function dr_ste_v3_set_insert_hdr`, `function dr_ste_v3_set_remove_hdr`, `function dr_ste_v3_set_action_decap_l3_list`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.