drivers/net/ethernet/mellanox/mlx5/core/steering/sws/mlx5_ifc_dr.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/mlx5_ifc_dr.h

File Facts

System: Linux kernel
Corpus path: drivers/net/ethernet/mellanox/mlx5/core/steering/sws/mlx5_ifc_dr.h
Extension: .h
Size: 15576 bytes
Lines: 644
Domain: Driver Families
Bucket: drivers/net
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

No C-style include directives detected by the generator.

Detected Declarations

struct mlx5_ifc_ste_general_bits
struct mlx5_ifc_ste_sx_transmit_bits
struct mlx5_ifc_ste_rx_steering_mult_bits
struct mlx5_ifc_ste_modify_packet_bits
struct mlx5_ifc_ste_eth_l2_src_bits
struct mlx5_ifc_ste_eth_l2_dst_bits
struct mlx5_ifc_ste_eth_l2_src_dst_bits
struct mlx5_ifc_ste_eth_l3_ipv4_5_tuple_bits
struct mlx5_ifc_ste_eth_l3_ipv6_dst_bits
struct mlx5_ifc_ste_eth_l2_tnl_bits
struct mlx5_ifc_ste_eth_l3_ipv6_src_bits
struct mlx5_ifc_ste_eth_l3_ipv4_misc_bits
struct mlx5_ifc_ste_eth_l4_bits
struct mlx5_ifc_ste_eth_l4_misc_bits
struct mlx5_ifc_ste_mpls_bits
struct mlx5_ifc_ste_register_0_bits
struct mlx5_ifc_ste_register_1_bits
struct mlx5_ifc_ste_gre_bits
struct mlx5_ifc_ste_flex_parser_0_bits
struct mlx5_ifc_ste_flex_parser_1_bits
struct mlx5_ifc_ste_flex_parser_ok_bits
struct mlx5_ifc_ste_flex_parser_tnl_bits
struct mlx5_ifc_ste_flex_parser_tnl_vxlan_gpe_bits
struct mlx5_ifc_ste_flex_parser_tnl_geneve_bits
struct mlx5_ifc_ste_flex_parser_tnl_gtpu_bits
struct mlx5_ifc_ste_tunnel_header_bits
struct mlx5_ifc_ste_general_purpose_bits
struct mlx5_ifc_ste_src_gvmi_qp_bits
struct mlx5_ifc_l2_hdr_bits
struct mlx5_ifc_dr_action_hw_set_bits
struct mlx5_ifc_dr_action_hw_copy_bits
struct mlx5_ifc_ste_aso_flow_meter_action_bits
struct mlx5_ifc_ste_double_action_aso_v1_bits
struct mlx5_ifc_ste_single_action_remove_header_v3_bits
struct mlx5_ifc_ste_single_action_remove_header_size_v3_bits
struct mlx5_ifc_ste_double_action_insert_with_inline_v3_bits
struct mlx5_ifc_ste_double_action_insert_with_ptr_v3_bits

Annotated Snippet

struct mlx5_ifc_ste_general_bits {
	u8         entry_type[0x4];
	u8         reserved_at_4[0x4];
	u8         entry_sub_type[0x8];
	u8         byte_mask[0x10];

	u8         next_table_base_63_48[0x10];
	u8         next_lu_type[0x8];
	u8         next_table_base_39_32_size[0x8];

	u8         next_table_base_31_5_size[0x1b];
	u8         linear_hash_enable[0x1];
	u8         reserved_at_5c[0x2];
	u8         next_table_rank[0x2];

	u8         reserved_at_60[0xa0];
	u8         tag_value[0x60];
	u8         bit_mask[0x60];
};

struct mlx5_ifc_ste_sx_transmit_bits {
	u8         entry_type[0x4];
	u8         reserved_at_4[0x4];
	u8         entry_sub_type[0x8];
	u8         byte_mask[0x10];

	u8         next_table_base_63_48[0x10];
	u8         next_lu_type[0x8];
	u8         next_table_base_39_32_size[0x8];

	u8         next_table_base_31_5_size[0x1b];
	u8         linear_hash_enable[0x1];
	u8         reserved_at_5c[0x2];
	u8         next_table_rank[0x2];

	u8         sx_wire[0x1];
	u8         sx_func_lb[0x1];
	u8         sx_sniffer[0x1];
	u8         sx_wire_enable[0x1];
	u8         sx_func_lb_enable[0x1];
	u8         sx_sniffer_enable[0x1];
	u8         action_type[0x3];
	u8         reserved_at_69[0x1];
	u8         action_description[0x6];
	u8         gvmi[0x10];

	u8         encap_pointer_vlan_data[0x20];

	u8         loopback_syndome_en[0x8];
	u8         loopback_syndome[0x8];
	u8         counter_trigger[0x10];

	u8         miss_address_63_48[0x10];
	u8         counter_trigger_23_16[0x8];
	u8         miss_address_39_32[0x8];

	u8         miss_address_31_6[0x1a];
	u8         learning_point[0x1];
	u8         go_back[0x1];
	u8         match_polarity[0x1];
	u8         mask_mode[0x1];
	u8         miss_rank[0x2];
};

struct mlx5_ifc_ste_rx_steering_mult_bits {
	u8         entry_type[0x4];
	u8         reserved_at_4[0x4];
	u8         entry_sub_type[0x8];
	u8         byte_mask[0x10];

	u8         next_table_base_63_48[0x10];
	u8         next_lu_type[0x8];
	u8         next_table_base_39_32_size[0x8];

	u8         next_table_base_31_5_size[0x1b];
	u8         linear_hash_enable[0x1];
	u8         reserved_at_[0x2];
	u8         next_table_rank[0x2];

	u8         member_count[0x10];
	u8         gvmi[0x10];

	u8         qp_list_pointer[0x20];

	u8         reserved_at_a0[0x1];
	u8         tunneling_action[0x3];
	u8         action_description[0x4];
	u8         reserved_at_a8[0x8];
	u8         counter_trigger_15_0[0x10];

Annotation

Detected declarations: `struct mlx5_ifc_ste_general_bits`, `struct mlx5_ifc_ste_sx_transmit_bits`, `struct mlx5_ifc_ste_rx_steering_mult_bits`, `struct mlx5_ifc_ste_modify_packet_bits`, `struct mlx5_ifc_ste_eth_l2_src_bits`, `struct mlx5_ifc_ste_eth_l2_dst_bits`, `struct mlx5_ifc_ste_eth_l2_src_dst_bits`, `struct mlx5_ifc_ste_eth_l3_ipv4_5_tuple_bits`, `struct mlx5_ifc_ste_eth_l3_ipv6_dst_bits`, `struct mlx5_ifc_ste_eth_l2_tnl_bits`.
Atlas domain: Driver Families / drivers/net.
Implementation status: source implementation candidate.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.