drivers/net/ethernet/mellanox/mlxsw/reg.h

File Facts

System

Linux kernel

Corpus path

drivers/net/ethernet/mellanox/mlxsw/reg.h

Extension

.h

Size

388714 bytes

Lines

13220

Domain

Driver Families

Bucket

drivers/net

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/kernel.h
• linux/string.h
• linux/bitops.h
• linux/if_vlan.h
• item.h
• port.h

Detected Declarations

• struct mlxsw_reg_info
• enum mlxsw_reg_sfd_op
• enum mlxsw_reg_sfd_rec_type
• enum mlxsw_reg_sfd_rec_policy
• enum mlxsw_reg_sfd_rec_action
• enum mlxsw_reg_sfd_uc_tunnel_protocol
• enum mlxsw_reg_tunnel_port
• enum mlxsw_reg_sfn_rec_type
• enum mlxsw_reg_sfn_uc_tunnel_protocol
• enum mlxsw_reg_spms_state
• enum mlxsw_reg_sfgc_type
• enum mlxsw_reg_bridge_type
• enum mlxsw_flood_table_type
• enum mlxsw_reg_sfdf_flush_type
• enum mlxsw_reg_sldr_op
• enum mlxsw_reg_slcr_pp
• enum mlxsw_reg_slcr_type
• enum mlxsw_reg_slcor_col
• enum mlxsw_reg_spmlr_learn_mode
• enum mlxsw_reg_svfa_mt
• enum mlxsw_reg_spvtr_ipvid_mode
• enum mlxsw_reg_spvtr_epvid_mode
• enum mlxsw_reg_sfmr_op
• enum mlxsw_reg_pxbt_e
• enum mlxsw_reg_pxbt_op
• enum mlxsw_reg_ptar_op
• enum mlxsw_reg_ptar_key_type
• enum mlxsw_reg_prcr_op
• enum mlxsw_reg_pemrbt_protocol
• enum mlxsw_reg_ptce2_op
• enum mlxsw_reg_perpt_key_size
• enum mlxsw_reg_ptce3_op
• enum mlxsw_reg_qpts_trust_state
• enum mlxsw_reg_qpcr_g
• enum mlxsw_reg_qpcr_ir_units
• enum mlxsw_reg_qpcr_rate_type
• enum mlxsw_reg_qpcr_action
• enum mlxsw_reg_qeec_hr
• enum mlxsw_reg_qpsc_port_speed
• enum mlxsw_reg_ptys_connector_type
• enum mlxsw_reg_ppcnt_grp
• enum mlxsw_reg_pmaos_admin_status
• enum mlxsw_reg_pmaos_e
• enum mlxsw_reg_pmtdb_status
• enum mlxsw_reg_pmecr_e
• enum mlxsw_reg_pmpe_module_status
• enum mlxsw_reg_pddr_page_select
• enum mlxsw_reg_pddr_trblsh_group_opcode

Annotated Snippet

struct mlxsw_reg_info {
	u16 id;
	u16 len; /* In u8 */
	const char *name;
};

#define MLXSW_REG_DEFINE(_name, _id, _len)				\
static const struct mlxsw_reg_info mlxsw_reg_##_name = {		\
	.id = _id,							\
	.len = _len,							\
	.name = #_name,							\
}

#define MLXSW_REG(type) (&mlxsw_reg_##type)
#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)

/* SGCR - Switch General Configuration Register
 * --------------------------------------------
 * This register is used for configuration of the switch capabilities.
 */
#define MLXSW_REG_SGCR_ID 0x2000
#define MLXSW_REG_SGCR_LEN 0x10

MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);

/* reg_sgcr_lag_lookup_pgt_base
 * Base address used for lookup in PGT table
 * Supported when CONFIG_PROFILE.lag_mode = 1
 * Note: when IGCR.ddd_lag_mode=0, the address shall be aligned to 8 entries.
 * Access: RW
 */
MLXSW_ITEM32(reg, sgcr, lag_lookup_pgt_base, 0x0C, 0, 16);

static inline void mlxsw_reg_sgcr_pack(char *payload, u16 lag_lookup_pgt_base)
{
	MLXSW_REG_ZERO(sgcr, payload);
	mlxsw_reg_sgcr_lag_lookup_pgt_base_set(payload, lag_lookup_pgt_base);
}

/* SPAD - Switch Physical Address Register
 * ---------------------------------------
 * The SPAD register configures the switch physical MAC address.
 */
#define MLXSW_REG_SPAD_ID 0x2002
#define MLXSW_REG_SPAD_LEN 0x10

MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);

/* reg_spad_base_mac
 * Base MAC address for the switch partitions.
 * Per switch partition MAC address is equal to:
 * base_mac + swid
 * Access: RW
 */
MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);

/* SSPR - Switch System Port Record Register
 * -----------------------------------------
 * Configures the system port to local port mapping.
 */
#define MLXSW_REG_SSPR_ID 0x2008
#define MLXSW_REG_SSPR_LEN 0x8

MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);

/* reg_sspr_m
 * Master - if set, then the record describes the master system port.
 * This is needed in case a local port is mapped into several system ports
 * (for multipathing). That number will be reported as the source system
 * port when packets are forwarded to the CPU. Only one master port is allowed
 * per local port.
 *
 * Note: Must be set for Spectrum.
 * Access: RW
 */
MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);

/* reg_sspr_local_port
 * Local port number.
 *
 * Access: RW
 */
MLXSW_ITEM32_LP(reg, sspr, 0x00, 16, 0x00, 12);

/* reg_sspr_system_port
 * Unique identifier within the stacking domain that represents all the ports
 * that are available in the system (external ports).
 *
 * Currently, only single-ASIC configurations are supported, so we default to

Annotation

• Immediate include surface: `linux/kernel.h`, `linux/string.h`, `linux/bitops.h`, `linux/if_vlan.h`, `item.h`, `port.h`.
• Detected declarations: `struct mlxsw_reg_info`, `enum mlxsw_reg_sfd_op`, `enum mlxsw_reg_sfd_rec_type`, `enum mlxsw_reg_sfd_rec_policy`, `enum mlxsw_reg_sfd_rec_action`, `enum mlxsw_reg_sfd_uc_tunnel_protocol`, `enum mlxsw_reg_tunnel_port`, `enum mlxsw_reg_sfn_rec_type`, `enum mlxsw_reg_sfn_uc_tunnel_protocol`, `enum mlxsw_reg_spms_state`.
• Atlas domain: Driver Families / drivers/net.
• Implementation status: source implementation candidate.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.