drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_rgmii.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_rgmii.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_rgmii.c
Extension
.c
Size
7254 bytes
Lines
225
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0+
/* Microchip lan969x Switch driver
 *
 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries.
 */

#include "lan969x.h"

/* Tx clock selectors */
#define LAN969X_RGMII_TX_CLK_SEL_125MHZ 1  /* 1000Mbps */
#define LAN969X_RGMII_TX_CLK_SEL_25MHZ  2  /* 100Mbps */
#define LAN969X_RGMII_TX_CLK_SEL_2M5MHZ 3  /* 10Mbps */

/* Port speed selectors */
#define LAN969X_RGMII_SPEED_SEL_10 0   /* Select 10Mbps speed */
#define LAN969X_RGMII_SPEED_SEL_100 1  /* Select 100Mbps speed */
#define LAN969X_RGMII_SPEED_SEL_1000 2 /* Select 1000Mbps speed */

/* Clock delay selectors */
#define LAN969X_RGMII_CLK_DELAY_SEL_1_0_NS 2  /* Phase shift 45deg */
#define LAN969X_RGMII_CLK_DELAY_SEL_1_7_NS 3  /* Phase shift 77deg */
#define LAN969X_RGMII_CLK_DELAY_SEL_2_0_NS 4  /* Phase shift 90deg */
#define LAN969X_RGMII_CLK_DELAY_SEL_2_5_NS 5  /* Phase shift 112deg */
#define LAN969X_RGMII_CLK_DELAY_SEL_3_0_NS 6  /* Phase shift 135deg */
#define LAN969X_RGMII_CLK_DELAY_SEL_3_3_NS 7  /* Phase shift 147deg */

#define LAN969X_RGMII_PORT_START_IDX 28 /* Index of the first RGMII port */
#define LAN969X_RGMII_IFG_TX 4          /* TX Inter Frame Gap value */
#define LAN969X_RGMII_IFG_RX1 5         /* RX1 Inter Frame Gap value */
#define LAN969X_RGMII_IFG_RX2 1         /* RX2 Inter Frame Gap value */

#define RGMII_PORT_IDX(port) ((port)->portno - LAN969X_RGMII_PORT_START_IDX)

/* Get the tx clock selector based on the port speed. */
static int lan969x_rgmii_get_clk_sel(int speed)
{
	return (speed == SPEED_10  ? LAN969X_RGMII_TX_CLK_SEL_2M5MHZ :
		speed == SPEED_100 ? LAN969X_RGMII_TX_CLK_SEL_25MHZ :
				     LAN969X_RGMII_TX_CLK_SEL_125MHZ);
}

/* Get the port speed selector based on the port speed. */
static int lan969x_rgmii_get_speed_sel(int speed)
{
	return (speed == SPEED_10  ? LAN969X_RGMII_SPEED_SEL_10 :
		speed == SPEED_100 ? LAN969X_RGMII_SPEED_SEL_100 :
				     LAN969X_RGMII_SPEED_SEL_1000);
}

/* Get the clock delay selector based on the clock delay in picoseconds. */
static int lan969x_rgmii_get_clk_delay_sel(struct sparx5_port *port,
					   u32 delay_ps, u32 *clk_delay_sel)
{
	switch (delay_ps) {
	case 0:
		/* Hardware default selector. */
		*clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_2_5_NS;
		break;
	case 1000:
		*clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_1_0_NS;
		break;
	case 1700:
		*clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_1_7_NS;
		break;
	case 2000:
		*clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_2_0_NS;
		break;
	case 2500:
		*clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_2_5_NS;
		break;
	case 3000:
		*clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_3_0_NS;
		break;
	case 3300:
		*clk_delay_sel = LAN969X_RGMII_CLK_DELAY_SEL_3_3_NS;
		break;
	default:
		dev_err(port->sparx5->dev, "Invalid RGMII delay: %u", delay_ps);
		return -EINVAL;
	}

	return 0;
}

/* Configure the RGMII tx clock frequency. */
static void lan969x_rgmii_tx_clk_config(struct sparx5_port *port,
					struct sparx5_port_config *conf)
{
	u32 clk_sel = lan969x_rgmii_get_clk_sel(conf->speed);
	u32 idx = RGMII_PORT_IDX(port);

Annotation

Implementation Notes