drivers/net/ethernet/microchip/sparx5/sparx5_main.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/microchip/sparx5/sparx5_main.c

File Facts

System: Linux kernel
Corpus path: drivers/net/ethernet/microchip/sparx5/sparx5_main.c
Extension: .c
Size: 37282 bytes
Lines: 1126
Domain: Driver Families
Bucket: drivers/net
Inferred role: Driver Families: implementation source
Status: source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
Touches IRQ or DMA behavior; this matters for the representative real-device path.
Allocates kernel memory; connect allocation flags and lifetime to context constraints.
Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

linux/module.h
linux/device.h
linux/netdevice.h
linux/platform_device.h
linux/interrupt.h
linux/of.h
linux/of_net.h
linux/of_mdio.h
net/switchdev.h
linux/etherdevice.h
linux/io.h
linux/printk.h
linux/iopoll.h
linux/mfd/syscon.h
linux/regmap.h
linux/types.h
linux/reset.h
lan969x/lan969x.h
sparx5_main_regs.h
sparx5_main.h
sparx5_port.h
sparx5_qos.h
sparx5_vcap_ag_api.h
sparx5_vcap_impl.h

Detected Declarations

struct initial_port_config
struct sparx5_ram_config
function is_sparx5
function sparx5_init_features
function sparx5_has_feature
function sparx5_create_targets
function sparx5_create_port
function sparx5_init_ram
function sparx5_init_switchcore
function sparx5_init_coreclock
function qlim_wm
function sparx5_qlim_set
function sparx5_frame_io_init
function sparx5_frame_io_deinit
function sparx5_board_init
function sparx5_forwarding_init
function mchp_sparx5_probe
function for_each_available_child_of_node
function mchp_sparx5_remove

Annotated Snippet

struct initial_port_config {
	u32 portno;
	struct device_node *node;
	struct sparx5_port_config conf;
	struct phy *serdes;
};

struct sparx5_ram_config {
	void __iomem *init_reg;
	u32 init_val;
};

static const struct sparx5_main_io_resource sparx5_main_iomap[] =  {
	{ TARGET_CPU,                         0, 0 }, /* 0x600000000 */
	{ TARGET_FDMA,                  0x80000, 0 }, /* 0x600080000 */
	{ TARGET_PCEP,                 0x400000, 0 }, /* 0x600400000 */
	{ TARGET_DEV2G5,             0x10004000, 1 }, /* 0x610004000 */
	{ TARGET_DEV5G,              0x10008000, 1 }, /* 0x610008000 */
	{ TARGET_PCS5G_BR,           0x1000c000, 1 }, /* 0x61000c000 */
	{ TARGET_DEV2G5 +  1,        0x10010000, 1 }, /* 0x610010000 */
	{ TARGET_DEV5G +  1,         0x10014000, 1 }, /* 0x610014000 */
	{ TARGET_PCS5G_BR +  1,      0x10018000, 1 }, /* 0x610018000 */
	{ TARGET_DEV2G5 +  2,        0x1001c000, 1 }, /* 0x61001c000 */
	{ TARGET_DEV5G +  2,         0x10020000, 1 }, /* 0x610020000 */
	{ TARGET_PCS5G_BR +  2,      0x10024000, 1 }, /* 0x610024000 */
	{ TARGET_DEV2G5 +  6,        0x10028000, 1 }, /* 0x610028000 */
	{ TARGET_DEV5G +  6,         0x1002c000, 1 }, /* 0x61002c000 */
	{ TARGET_PCS5G_BR +  6,      0x10030000, 1 }, /* 0x610030000 */
	{ TARGET_DEV2G5 +  7,        0x10034000, 1 }, /* 0x610034000 */
	{ TARGET_DEV5G +  7,         0x10038000, 1 }, /* 0x610038000 */
	{ TARGET_PCS5G_BR +  7,      0x1003c000, 1 }, /* 0x61003c000 */
	{ TARGET_DEV2G5 +  8,        0x10040000, 1 }, /* 0x610040000 */
	{ TARGET_DEV5G +  8,         0x10044000, 1 }, /* 0x610044000 */
	{ TARGET_PCS5G_BR +  8,      0x10048000, 1 }, /* 0x610048000 */
	{ TARGET_DEV2G5 +  9,        0x1004c000, 1 }, /* 0x61004c000 */
	{ TARGET_DEV5G +  9,         0x10050000, 1 }, /* 0x610050000 */
	{ TARGET_PCS5G_BR +  9,      0x10054000, 1 }, /* 0x610054000 */
	{ TARGET_DEV2G5 + 10,        0x10058000, 1 }, /* 0x610058000 */
	{ TARGET_DEV5G + 10,         0x1005c000, 1 }, /* 0x61005c000 */
	{ TARGET_PCS5G_BR + 10,      0x10060000, 1 }, /* 0x610060000 */
	{ TARGET_DEV2G5 + 11,        0x10064000, 1 }, /* 0x610064000 */
	{ TARGET_DEV5G + 11,         0x10068000, 1 }, /* 0x610068000 */
	{ TARGET_PCS5G_BR + 11,      0x1006c000, 1 }, /* 0x61006c000 */
	{ TARGET_DEV2G5 + 12,        0x10070000, 1 }, /* 0x610070000 */
	{ TARGET_DEV10G,             0x10074000, 1 }, /* 0x610074000 */
	{ TARGET_PCS10G_BR,          0x10078000, 1 }, /* 0x610078000 */
	{ TARGET_DEV2G5 + 14,        0x1007c000, 1 }, /* 0x61007c000 */
	{ TARGET_DEV10G +  2,        0x10080000, 1 }, /* 0x610080000 */
	{ TARGET_PCS10G_BR +  2,     0x10084000, 1 }, /* 0x610084000 */
	{ TARGET_DEV2G5 + 15,        0x10088000, 1 }, /* 0x610088000 */
	{ TARGET_DEV10G +  3,        0x1008c000, 1 }, /* 0x61008c000 */
	{ TARGET_PCS10G_BR +  3,     0x10090000, 1 }, /* 0x610090000 */
	{ TARGET_DEV2G5 + 16,        0x10094000, 1 }, /* 0x610094000 */
	{ TARGET_DEV2G5 + 17,        0x10098000, 1 }, /* 0x610098000 */
	{ TARGET_DEV2G5 + 18,        0x1009c000, 1 }, /* 0x61009c000 */
	{ TARGET_DEV2G5 + 19,        0x100a0000, 1 }, /* 0x6100a0000 */
	{ TARGET_DEV2G5 + 20,        0x100a4000, 1 }, /* 0x6100a4000 */
	{ TARGET_DEV2G5 + 21,        0x100a8000, 1 }, /* 0x6100a8000 */
	{ TARGET_DEV2G5 + 22,        0x100ac000, 1 }, /* 0x6100ac000 */
	{ TARGET_DEV2G5 + 23,        0x100b0000, 1 }, /* 0x6100b0000 */
	{ TARGET_DEV2G5 + 32,        0x100b4000, 1 }, /* 0x6100b4000 */
	{ TARGET_DEV2G5 + 33,        0x100b8000, 1 }, /* 0x6100b8000 */
	{ TARGET_DEV2G5 + 34,        0x100bc000, 1 }, /* 0x6100bc000 */
	{ TARGET_DEV2G5 + 35,        0x100c0000, 1 }, /* 0x6100c0000 */
	{ TARGET_DEV2G5 + 36,        0x100c4000, 1 }, /* 0x6100c4000 */
	{ TARGET_DEV2G5 + 37,        0x100c8000, 1 }, /* 0x6100c8000 */
	{ TARGET_DEV2G5 + 38,        0x100cc000, 1 }, /* 0x6100cc000 */
	{ TARGET_DEV2G5 + 39,        0x100d0000, 1 }, /* 0x6100d0000 */
	{ TARGET_DEV2G5 + 40,        0x100d4000, 1 }, /* 0x6100d4000 */
	{ TARGET_DEV2G5 + 41,        0x100d8000, 1 }, /* 0x6100d8000 */
	{ TARGET_DEV2G5 + 42,        0x100dc000, 1 }, /* 0x6100dc000 */
	{ TARGET_DEV2G5 + 43,        0x100e0000, 1 }, /* 0x6100e0000 */
	{ TARGET_DEV2G5 + 44,        0x100e4000, 1 }, /* 0x6100e4000 */
	{ TARGET_DEV2G5 + 45,        0x100e8000, 1 }, /* 0x6100e8000 */
	{ TARGET_DEV2G5 + 46,        0x100ec000, 1 }, /* 0x6100ec000 */
	{ TARGET_DEV2G5 + 47,        0x100f0000, 1 }, /* 0x6100f0000 */
	{ TARGET_DEV2G5 + 57,        0x100f4000, 1 }, /* 0x6100f4000 */
	{ TARGET_DEV25G +  1,        0x100f8000, 1 }, /* 0x6100f8000 */
	{ TARGET_PCS25G_BR +  1,     0x100fc000, 1 }, /* 0x6100fc000 */
	{ TARGET_DEV2G5 + 59,        0x10104000, 1 }, /* 0x610104000 */
	{ TARGET_DEV25G +  3,        0x10108000, 1 }, /* 0x610108000 */
	{ TARGET_PCS25G_BR +  3,     0x1010c000, 1 }, /* 0x61010c000 */
	{ TARGET_DEV2G5 + 60,        0x10114000, 1 }, /* 0x610114000 */
	{ TARGET_DEV25G +  4,        0x10118000, 1 }, /* 0x610118000 */
	{ TARGET_PCS25G_BR +  4,     0x1011c000, 1 }, /* 0x61011c000 */
	{ TARGET_DEV2G5 + 64,        0x10124000, 1 }, /* 0x610124000 */
	{ TARGET_DEV5G + 12,         0x10128000, 1 }, /* 0x610128000 */
	{ TARGET_PCS5G_BR + 12,      0x1012c000, 1 }, /* 0x61012c000 */
	{ TARGET_PORT_CONF,          0x10130000, 1 }, /* 0x610130000 */
	{ TARGET_DEV2G5 +  3,        0x10404000, 1 }, /* 0x610404000 */

Annotation

Immediate include surface: `linux/module.h`, `linux/device.h`, `linux/netdevice.h`, `linux/platform_device.h`, `linux/interrupt.h`, `linux/of.h`, `linux/of_net.h`, `linux/of_mdio.h`.
Detected declarations: `struct initial_port_config`, `struct sparx5_ram_config`, `function is_sparx5`, `function sparx5_init_features`, `function sparx5_has_feature`, `function sparx5_create_targets`, `function sparx5_create_port`, `function sparx5_init_ram`, `function sparx5_init_switchcore`, `function sparx5_init_coreclock`.
Atlas domain: Driver Families / drivers/net.
Implementation status: source implementation candidate.
Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.