drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h
Extension
.h
Size
354758 bytes
Lines
8259
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef _SPARX5_MAIN_REGS_H_
#define _SPARX5_MAIN_REGS_H_

#include <linux/bitfield.h>
#include <linux/types.h>
#include <linux/bug.h>

#include "sparx5_regs.h"

enum sparx5_target {
	TARGET_ANA_AC = 1,
	TARGET_ANA_ACL = 2,
	TARGET_ANA_AC_POL = 4,
	TARGET_ANA_AC_SDLB = 5,
	TARGET_ANA_CL = 6,
	TARGET_ANA_L2 = 7,
	TARGET_ANA_L3 = 8,
	TARGET_ASM = 9,
	TARGET_CLKGEN = 11,
	TARGET_CPU = 12,
	TARGET_DEV10G = 17,
	TARGET_DEV25G = 29,
	TARGET_DEV2G5 = 37,
	TARGET_DEV5G = 102,
	TARGET_DSM = 115,
	TARGET_EACL = 116,
	TARGET_FDMA = 117,
	TARGET_GCB = 118,
	TARGET_HSCH = 119,
	TARGET_HSIO_WRAP = 120,
	TARGET_LRN = 122,
	TARGET_PCEP = 129,
	TARGET_PCS10G_BR = 132,
	TARGET_PCS25G_BR = 144,
	TARGET_PCS5G_BR = 160,
	TARGET_PORT_CONF = 173,
	TARGET_PTP = 174,
	TARGET_QFWD = 175,
	TARGET_QRES = 176,
	TARGET_QS = 177,
	TARGET_QSYS = 178,
	TARGET_REW = 179,
	TARGET_VCAP_ES0 = 323,
	TARGET_VCAP_ES2 = 324,
	TARGET_VCAP_SUPER = 326,
	TARGET_VOP = 327,
	TARGET_XQS = 331,
	TARGET_DEVRGMII = 392,
	NUM_TARGETS = 517
};

/* sparx5_main.c
 *
 * This is used by the register macros to access chip differences (if any) in:
 * target size, register address, register count, group address, group count,
 * group size, field position and field size.
 */
extern const struct sparx5_regs *regs;

/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
#define spx5_field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
#define spx5_field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))

#define __REG(...)    __VA_ARGS__

/* ANA_AC:RAM_CTRL:RAM_INIT */
#define ANA_AC_RAM_INIT                                                        \
	__REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_RAM_CTRL], 0, 1, 4, 0,\
	      0, 1, 4)

#define ANA_AC_RAM_INIT_RAM_INIT                 BIT(1)
#define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\
	FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
#define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\
	FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x)

#define ANA_AC_RAM_INIT_RAM_CFG_HOOK             BIT(0)
#define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\
	FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
#define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\
	FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)

/* ANA_AC:PS_COMMON:OWN_UPSID */
#define ANA_AC_OWN_UPSID(r)                                                    \
	__REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PS_COMMON], 0, 1, 352,\
	      52, r, regs->rcnt[RC_ANA_AC_OWN_UPSID], 4)

#define ANA_AC_OWN_UPSID_OWN_UPSID               GENMASK(4, 0)
#define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\
	FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x)

Annotation

Implementation Notes