drivers/net/ethernet/microchip/sparx5/sparx5_port.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/microchip/sparx5/sparx5_port.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/microchip/sparx5/sparx5_port.c- Extension
.c- Size
- 40337 bytes
- Lines
- 1426
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hlinux/phy/phy.hnet/dcbnl.hsparx5_main_regs.hsparx5_main.hsparx5_port.h
Detected Declarations
enum port_errorfunction decode_sgmii_wordfunction decode_cl37_wordfunction sparx5_get_dev2g5_statusfunction sparx5_get_sfi_statusfunction sparx5_get_port_statusfunction sparx5_port_errorfunction sparx5_port_verify_speedfunction sparx5_dev_changefunction sparx5_port_flush_pollfunction sparx5_port_disablefunction sparx5_port_fifo_szfunction sparx5_port_mux_setfunction sparx5_port_max_tags_setfunction sparx5_port_fwd_urgfunction sparx5_wm_encfunction sparx5_port_fc_setupfunction sparx5_get_aneg_wordfunction sparx5_serdes_setfunction sparx5_port_pcs_low_setfunction sparx5_port_pcs_high_setfunction sparx5_dev_switchfunction sparx5_port_config_low_setfunction sparx5_port_pcs_setfunction sparx5_port_configfunction sparx5_port_initfunction sparx5_port_enablefunction sparx5_port_qos_setfunction sparx5_port_qos_pcp_rewr_setfunction sparx5_port_qos_pcp_setfunction sparx5_port_qos_dscp_rewr_mode_setfunction sparx5_port_qos_dscp_rewr_setfunction sparx5_port_qos_dscp_setfunction sparx5_port_qos_default_setfunction sparx5_get_internal_port
Annotated Snippet
if (port->conf.portmode == PHY_INTERFACE_MODE_SGMII) {
decode_sgmii_word(lp_adv, status);
} else {
value = spx5_rd(sparx5, DEV2G5_PCS1G_ANEG_CFG(portno));
ld_adv = DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(value);
decode_cl37_word(lp_adv, ld_adv, status);
}
}
return 0;
}
static int sparx5_get_sfi_status(struct sparx5 *sparx5,
struct sparx5_port *port,
struct sparx5_port_status *status)
{
bool high_speed_dev = sparx5_is_baser(port->conf.portmode);
u32 portno = port->portno;
u32 value, dev, tinst;
void __iomem *inst;
if (!high_speed_dev) {
netdev_err(port->ndev, "error: low speed and SFI mode\n");
return -EINVAL;
}
dev = sparx5_to_high_dev(sparx5, portno);
tinst = sparx5_port_dev_index(sparx5, portno);
inst = spx5_inst_get(sparx5, dev, tinst);
value = spx5_inst_rd(inst, DEV10G_MAC_TX_MONITOR_STICKY(0));
if (value != DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY) {
/* The link is or has been down. Clear the sticky bit */
status->link_down = 1;
spx5_inst_wr(0xffffffff, inst, DEV10G_MAC_TX_MONITOR_STICKY(0));
value = spx5_inst_rd(inst, DEV10G_MAC_TX_MONITOR_STICKY(0));
}
status->link = (value == DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY);
status->duplex = DUPLEX_FULL;
if (port->conf.portmode == PHY_INTERFACE_MODE_5GBASER)
status->speed = SPEED_5000;
else if (port->conf.portmode == PHY_INTERFACE_MODE_10GBASER)
status->speed = SPEED_10000;
else
status->speed = SPEED_25000;
return 0;
}
/* Get link status of 1000Base-X/in-band and SFI ports.
*/
int sparx5_get_port_status(struct sparx5 *sparx5,
struct sparx5_port *port,
struct sparx5_port_status *status)
{
memset(status, 0, sizeof(*status));
status->speed = port->conf.speed;
if (port->conf.power_down) {
status->link = false;
return 0;
}
switch (port->conf.portmode) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_QSGMII:
case PHY_INTERFACE_MODE_1000BASEX:
case PHY_INTERFACE_MODE_2500BASEX:
return sparx5_get_dev2g5_status(sparx5, port, status);
case PHY_INTERFACE_MODE_5GBASER:
case PHY_INTERFACE_MODE_10GBASER:
case PHY_INTERFACE_MODE_25GBASER:
return sparx5_get_sfi_status(sparx5, port, status);
case PHY_INTERFACE_MODE_NA:
return 0;
default:
netdev_err(port->ndev, "Status not supported");
return -ENODEV;
}
return 0;
}
static int sparx5_port_error(struct sparx5_port *port,
struct sparx5_port_config *conf,
enum port_error errtype)
{
switch (errtype) {
case SPX5_PERR_SPEED:
netdev_err(port->ndev,
"Interface does not support speed: %u: for %s\n",
conf->speed, phy_modes(conf->portmode));
break;
case SPX5_PERR_IFTYPE:
Annotation
- Immediate include surface: `linux/module.h`, `linux/phy/phy.h`, `net/dcbnl.h`, `sparx5_main_regs.h`, `sparx5_main.h`, `sparx5_port.h`.
- Detected declarations: `enum port_error`, `function decode_sgmii_word`, `function decode_cl37_word`, `function sparx5_get_dev2g5_status`, `function sparx5_get_sfi_status`, `function sparx5_get_port_status`, `function sparx5_port_error`, `function sparx5_port_verify_speed`, `function sparx5_dev_change`, `function sparx5_port_flush_poll`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.