drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/microchip/sparx5/sparx5_vcap_impl.c- Extension
.c- Size
- 61718 bytes
- Lines
- 2102
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
vcap_api_debugfs.hsparx5_main_regs.hsparx5_main.hsparx5_vcap_impl.hsparx5_vcap_ag_api.hsparx5_vcap_debugfs.h
Detected Declarations
function sparx5_vcap_type_errfunction sparx5_vcap_wait_super_updatefunction sparx5_vcap_wait_es0_updatefunction sparx5_vcap_wait_es2_updatefunction _sparx5_vcap_range_initfunction sparx5_vcap_block_initfunction sparx5_vcap_is0_is_first_chainfunction sparx5_vcap_is2_is_first_chainfunction sparx5_vcap_es2_is_first_chainfunction sparx5_vcap_add_ingress_range_port_maskfunction sparx5_vcap_add_wide_port_maskfunction sparx5_vcap_add_egress_range_port_maskfunction sparx5_vcap_is0_cid_to_lookupfunction sparx5_vcap_is2_cid_to_lookupfunction sparx5_vcap_es2_cid_to_lookupfunction sparx5_vcap_is0_get_port_etype_keysetsfunction sparx5_vcap_is0_get_port_keysetsfunction sparx5_vcap_is2_get_port_keysetsfunction sparx5_vcap_es2_get_port_ipv4_keysetsfunction sparx5_vcap_es0_get_port_keysetsfunction sparx5_vcap_es2_get_port_keysetsfunction sparx5_vcap_get_port_keysetfunction sparx5_vcap_is_known_etypefunction sparx5_vcap_validate_keysetfunction sparx5_vcap_ingress_add_default_fieldsfunction sparx5_vcap_es0_add_default_fieldsfunction sparx5_vcap_es2_add_default_fieldsfunction sparx5_vcap_add_default_fieldsfunction sparx5_vcap_cache_erasefunction sparx5_vcap_is0_cache_writefunction sparx5_vcap_is2_cache_writefunction sparx5_es0_write_esdx_counterfunction sparx5_vcap_es0_cache_writefunction sparx5_vcap_es2_cache_writefunction sparx5_vcap_cache_writefunction sparx5_vcap_is0_cache_readfunction sparx5_vcap_is2_cache_readfunction sparx5_es0_read_esdx_counterfunction sparx5_vcap_es0_cache_readfunction sparx5_vcap_es2_cache_readfunction sparx5_vcap_cache_readfunction sparx5_vcap_range_initfunction sparx5_vcap_super_updatefunction sparx5_vcap_es0_updatefunction sparx5_vcap_es2_updatefunction sparx5_vcap_updatefunction sparx5_vcap_super_movefunction sparx5_vcap_es0_move
Annotated Snippet
switch (ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_GET(value)) {
case VCAP_IS0_PS_ETYPE_DEFAULT:
sparx5_vcap_is0_get_port_etype_keysets(keysetlist,
value);
break;
case VCAP_IS0_PS_ETYPE_NORMAL_7TUPLE:
vcap_keyset_list_add(keysetlist,
VCAP_KFS_NORMAL_7TUPLE);
break;
case VCAP_IS0_PS_ETYPE_NORMAL_5TUPLE_IP4:
vcap_keyset_list_add(keysetlist,
VCAP_KFS_NORMAL_5TUPLE_IP4);
break;
}
if (l3_proto == ETH_P_ALL || l3_proto == ETH_P_IPV6)
switch (ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_GET(value)) {
case VCAP_IS0_PS_ETYPE_DEFAULT:
sparx5_vcap_is0_get_port_etype_keysets(keysetlist,
value);
break;
case VCAP_IS0_PS_ETYPE_NORMAL_7TUPLE:
vcap_keyset_list_add(keysetlist,
VCAP_KFS_NORMAL_7TUPLE);
break;
case VCAP_IS0_PS_ETYPE_NORMAL_5TUPLE_IP4:
vcap_keyset_list_add(keysetlist,
VCAP_KFS_NORMAL_5TUPLE_IP4);
break;
}
if (l3_proto != ETH_P_IP && l3_proto != ETH_P_IPV6)
sparx5_vcap_is0_get_port_etype_keysets(keysetlist, value);
return 0;
}
/* Return the list of keysets for the vcap port configuration */
static int sparx5_vcap_is2_get_port_keysets(struct net_device *ndev,
int lookup,
struct vcap_keyset_list *keysetlist,
u16 l3_proto)
{
struct sparx5_port *port = netdev_priv(ndev);
struct sparx5 *sparx5 = port->sparx5;
int portno = port->portno;
u32 value;
value = spx5_rd(sparx5, ANA_ACL_VCAP_S2_KEY_SEL(portno, lookup));
/* Collect all keysets for the port in a list */
if (l3_proto == ETH_P_ALL || l3_proto == ETH_P_ARP) {
switch (ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(value)) {
case VCAP_IS2_PS_ARP_MAC_ETYPE:
vcap_keyset_list_add(keysetlist, VCAP_KFS_MAC_ETYPE);
break;
case VCAP_IS2_PS_ARP_ARP:
vcap_keyset_list_add(keysetlist, VCAP_KFS_ARP);
break;
}
}
if (l3_proto == ETH_P_ALL || l3_proto == ETH_P_IP) {
switch (ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_GET(value)) {
case VCAP_IS2_PS_IPV4_UC_MAC_ETYPE:
vcap_keyset_list_add(keysetlist, VCAP_KFS_MAC_ETYPE);
break;
case VCAP_IS2_PS_IPV4_UC_IP4_TCP_UDP_OTHER:
vcap_keyset_list_add(keysetlist, VCAP_KFS_IP4_TCP_UDP);
vcap_keyset_list_add(keysetlist, VCAP_KFS_IP4_OTHER);
break;
case VCAP_IS2_PS_IPV4_UC_IP_7TUPLE:
vcap_keyset_list_add(keysetlist, VCAP_KFS_IP_7TUPLE);
break;
}
switch (ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_GET(value)) {
case VCAP_IS2_PS_IPV4_MC_MAC_ETYPE:
vcap_keyset_list_add(keysetlist, VCAP_KFS_MAC_ETYPE);
break;
case VCAP_IS2_PS_IPV4_MC_IP4_TCP_UDP_OTHER:
vcap_keyset_list_add(keysetlist, VCAP_KFS_IP4_TCP_UDP);
vcap_keyset_list_add(keysetlist, VCAP_KFS_IP4_OTHER);
break;
case VCAP_IS2_PS_IPV4_MC_IP_7TUPLE:
vcap_keyset_list_add(keysetlist, VCAP_KFS_IP_7TUPLE);
break;
}
}
if (l3_proto == ETH_P_ALL || l3_proto == ETH_P_IPV6) {
Annotation
- Immediate include surface: `vcap_api_debugfs.h`, `sparx5_main_regs.h`, `sparx5_main.h`, `sparx5_vcap_impl.h`, `sparx5_vcap_ag_api.h`, `sparx5_vcap_debugfs.h`.
- Detected declarations: `function sparx5_vcap_type_err`, `function sparx5_vcap_wait_super_update`, `function sparx5_vcap_wait_es0_update`, `function sparx5_vcap_wait_es2_update`, `function _sparx5_vcap_range_init`, `function sparx5_vcap_block_init`, `function sparx5_vcap_is0_is_first_chain`, `function sparx5_vcap_is2_is_first_chain`, `function sparx5_vcap_es2_is_first_chain`, `function sparx5_vcap_add_ingress_range_port_mask`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.