drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/oki-semi/pch_gbe/pch_gbe.h
Extension
.h
Size
21443 bytes
Lines
625
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct pch_gbe_regs_mac_adr {
	u32 high;
	u32 low;
};
/**
 * pch_udc_regs - Structure holding values of MAC registers
 */
struct pch_gbe_regs {
	u32 INT_ST;
	u32 INT_EN;
	u32 MODE;
	u32 RESET;
	u32 TCPIP_ACC;
	u32 EX_LIST;
	u32 INT_ST_HOLD;
	u32 PHY_INT_CTRL;
	u32 MAC_RX_EN;
	u32 RX_FCTRL;
	u32 PAUSE_REQ;
	u32 RX_MODE;
	u32 TX_MODE;
	u32 RX_FIFO_ST;
	u32 TX_FIFO_ST;
	u32 TX_FID;
	u32 TX_RESULT;
	u32 PAUSE_PKT1;
	u32 PAUSE_PKT2;
	u32 PAUSE_PKT3;
	u32 PAUSE_PKT4;
	u32 PAUSE_PKT5;
	u32 reserve[2];
	struct pch_gbe_regs_mac_adr mac_adr[16];
	u32 ADDR_MASK;
	u32 MIIM;
	u32 MAC_ADDR_LOAD;
	u32 RGMII_ST;
	u32 RGMII_CTRL;
	u32 reserve3[3];
	u32 DMA_CTRL;
	u32 reserve4[3];
	u32 RX_DSC_BASE;
	u32 RX_DSC_SIZE;
	u32 RX_DSC_HW_P;
	u32 RX_DSC_HW_P_HLD;
	u32 RX_DSC_SW_P;
	u32 reserve5[3];
	u32 TX_DSC_BASE;
	u32 TX_DSC_SIZE;
	u32 TX_DSC_HW_P;
	u32 TX_DSC_HW_P_HLD;
	u32 TX_DSC_SW_P;
	u32 reserve6[3];
	u32 RX_DMA_ST;
	u32 TX_DMA_ST;
	u32 reserve7[2];
	u32 WOL_ST;
	u32 WOL_CTRL;
	u32 WOL_ADDR_MASK;
};

/* Interrupt Status */
/* Interrupt Status Hold */
/* Interrupt Enable */
#define PCH_GBE_INT_RX_DMA_CMPLT  0x00000001 /* Receive DMA Transfer Complete */
#define PCH_GBE_INT_RX_VALID      0x00000002 /* MAC Normal Receive Complete */
#define PCH_GBE_INT_RX_FRAME_ERR  0x00000004 /* Receive frame error */
#define PCH_GBE_INT_RX_FIFO_ERR   0x00000008 /* Receive FIFO Overflow */
#define PCH_GBE_INT_RX_DMA_ERR    0x00000010 /* Receive DMA Transfer Error */
#define PCH_GBE_INT_RX_DSC_EMP    0x00000020 /* Receive Descriptor Empty */
#define PCH_GBE_INT_TX_CMPLT      0x00000100 /* MAC Transmission Complete */
#define PCH_GBE_INT_TX_DMA_CMPLT  0x00000200 /* DMA Transfer Complete */
#define PCH_GBE_INT_TX_FIFO_ERR   0x00000400 /* Transmission FIFO underflow. */
#define PCH_GBE_INT_TX_DMA_ERR    0x00000800 /* Transmission DMA Error */
#define PCH_GBE_INT_PAUSE_CMPLT   0x00001000 /* Pause Transmission complete */
#define PCH_GBE_INT_MIIM_CMPLT    0x00010000 /* MIIM I/F Read completion */
#define PCH_GBE_INT_PHY_INT       0x00100000 /* Interruption from PHY */
#define PCH_GBE_INT_WOL_DET       0x01000000 /* Wake On LAN Event detection. */
#define PCH_GBE_INT_TCPIP_ERR     0x10000000 /* TCP/IP Accelerator Error */

/* Mode */
#define PCH_GBE_MODE_MII_ETHER      0x00000000  /* GIGA Ethernet Mode [MII] */
#define PCH_GBE_MODE_GMII_ETHER     0x80000000  /* GIGA Ethernet Mode [GMII] */
#define PCH_GBE_MODE_HALF_DUPLEX    0x00000000  /* Duplex Mode [half duplex] */
#define PCH_GBE_MODE_FULL_DUPLEX    0x40000000  /* Duplex Mode [full duplex] */
#define PCH_GBE_MODE_FR_BST         0x04000000  /* Frame bursting is done */

/* Reset */
#define PCH_GBE_ALL_RST         0x80000000  /* All reset */
#define PCH_GBE_TX_RST          0x00008000  /* TX MAC, TX FIFO, TX DMA reset */
#define PCH_GBE_RX_RST          0x00004000  /* RX MAC, RX FIFO, RX DMA reset */

Annotation

Implementation Notes