drivers/net/ethernet/pensando/ionic/ionic_lif.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/pensando/ionic/ionic_lif.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/pensando/ionic/ionic_lif.h- Extension
.h- Size
- 10922 bytes
- Lines
- 414
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/ptp_clock_kernel.hlinux/timecounter.hlinux/net_tstamp.hlinux/dim.hlinux/pci.hionic_rx_filter.hionic_api.h
Detected Declarations
struct ionic_tx_statsstruct ionic_rx_statsstruct ionic_qcqstruct ionic_deferred_workstruct ionic_deferredstruct ionic_lif_sw_statsstruct ionic_qtype_infostruct ionic_phcstruct ionic_lifstruct ionic_phcstruct ionic_queue_paramsenum ionic_deferred_work_typeenum ionic_lif_state_flagsfunction ionic_init_queue_paramsfunction ionic_set_queue_paramsfunction ionic_coal_usec_to_hwfunction ionic_txq_hwstamp_enabledfunction ionic_lif_hwstamp_replayfunction ionic_hwstamp_getfunction ionic_lif_phc_ktimefunction ionic_lif_register_phc
Annotated Snippet
struct ionic_tx_stats {
u64 pkts;
u64 bytes;
u64 csum_none;
u64 csum;
u64 tso;
u64 tso_bytes;
u64 frags;
u64 vlan_inserted;
u64 clean;
u64 linearize;
u64 crc32_csum;
u64 dma_map_err;
u64 hwstamp_valid;
u64 hwstamp_invalid;
u64 xdp_frames;
};
struct ionic_rx_stats {
u64 pkts;
u64 bytes;
u64 csum_none;
u64 csum_complete;
u64 dropped;
u64 vlan_stripped;
u64 csum_error;
u64 dma_map_err;
u64 alloc_err;
u64 hwstamp_valid;
u64 hwstamp_invalid;
u64 xdp_drop;
u64 xdp_aborted;
u64 xdp_pass;
u64 xdp_tx;
u64 xdp_redirect;
};
#define IONIC_QCQ_F_INITED BIT(0)
#define IONIC_QCQ_F_SG BIT(1)
#define IONIC_QCQ_F_INTR BIT(2)
#define IONIC_QCQ_F_TX_STATS BIT(3)
#define IONIC_QCQ_F_RX_STATS BIT(4)
#define IONIC_QCQ_F_NOTIFYQ BIT(5)
#define IONIC_QCQ_F_CMB_RINGS BIT(6)
struct ionic_qcq {
void *q_base;
dma_addr_t q_base_pa;
u32 q_size;
u32 cq_size;
void *cq_base;
dma_addr_t cq_base_pa;
void *sg_base;
dma_addr_t sg_base_pa;
u32 sg_size;
unsigned int flags;
void __iomem *cmb_q_base;
phys_addr_t cmb_q_base_pa;
u32 cmb_q_size;
u32 cmb_pgid;
u32 cmb_order;
struct dim dim;
struct ionic_queue q;
struct ionic_cq cq;
struct napi_struct napi;
struct ionic_intr_info intr;
struct work_struct doorbell_napi_work;
struct dentry *dentry;
};
#define q_to_qcq(q) container_of(q, struct ionic_qcq, q)
#define q_to_tx_stats(q) (&(q)->lif->txqstats[(q)->index])
#define q_to_rx_stats(q) (&(q)->lif->rxqstats[(q)->index])
#define napi_to_qcq(napi) container_of(napi, struct ionic_qcq, napi)
#define napi_to_cq(napi) (&napi_to_qcq(napi)->cq)
enum ionic_deferred_work_type {
IONIC_DW_TYPE_RX_MODE,
IONIC_DW_TYPE_LINK_STATUS,
IONIC_DW_TYPE_LIF_RESET,
};
struct ionic_deferred_work {
struct list_head list;
enum ionic_deferred_work_type type;
union {
u8 addr[ETH_ALEN];
u8 fw_status;
};
};
Annotation
- Immediate include surface: `linux/ptp_clock_kernel.h`, `linux/timecounter.h`, `linux/net_tstamp.h`, `linux/dim.h`, `linux/pci.h`, `ionic_rx_filter.h`, `ionic_api.h`.
- Detected declarations: `struct ionic_tx_stats`, `struct ionic_rx_stats`, `struct ionic_qcq`, `struct ionic_deferred_work`, `struct ionic_deferred`, `struct ionic_lif_sw_stats`, `struct ionic_qtype_info`, `struct ionic_phc`, `struct ionic_lif`, `struct ionic_phc`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.