drivers/net/ethernet/qlogic/qed/qed_cxt.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/qlogic/qed/qed_cxt.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/qlogic/qed/qed_cxt.c- Extension
.c- Size
- 72899 bytes
- Lines
- 2572
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/types.hlinux/bitops.hlinux/dma-mapping.hlinux/errno.hlinux/kernel.hlinux/list.hlinux/log2.hlinux/pci.hlinux/slab.hlinux/string.hqed.hqed_cxt.hqed_dev_api.hqed_hsi.hqed_hw.hqed_init_ops.hqed_rdma.hqed_reg_addr.hqed_sriov.h
Detected Declarations
struct src_entstruct qed_cdu_iidsstruct qed_src_iidsstruct qed_tm_iidsfunction src_protofunction tm_cid_protofunction tm_tid_protofunction qed_cxt_cdu_iidsfunction qed_cxt_src_iidsfunction qed_cxt_tm_iidsfunction qed_cxt_qm_iidsfunction qed_cxt_set_srq_countfunction qed_cxt_get_ilt_page_sizefunction qed_cxt_xrc_srqs_per_pagefunction qed_cxt_get_total_srq_countfunction qed_cxt_set_proto_cid_countfunction qed_cxt_get_proto_cid_countfunction qed_cxt_get_proto_cid_startfunction qed_cxt_get_proto_tid_countfunction qed_cxt_set_proto_tid_countfunction qed_ilt_cli_blk_fillfunction qed_ilt_cli_adv_linefunction qed_ilt_get_dynamic_line_cntfunction qed_cxt_ilt_blk_resetfunction qed_cxt_cfg_ilt_computefunction qed_cxt_cfg_ilt_compute_excessfunction qed_cxt_src_t2_freefunction qed_cxt_t2_alloc_pagesfunction qed_cxt_src_t2_allocfunction qed_cxt_ilt_shadow_sizefunction qed_ilt_shadow_freefunction qed_ilt_blk_allocfunction qed_ilt_shadow_allocfunction for_each_ilt_valid_clientfunction qed_cid_map_freefunction qed_cid_map_alloc_singlefunction qed_cid_map_allocfunction qed_cxt_mngr_allocfunction qed_cxt_tables_allocfunction qed_cxt_mngr_freefunction qed_cxt_mngr_setupfunction qed_cdu_init_commonfunction qed_cdu_init_pffunction qed_qm_init_pffunction qed_cm_init_pffunction qed_dq_init_pffunction qed_ilt_bounds_initfunction qed_ilt_vf_bounds_init
Annotated Snippet
struct src_ent {
__u8 opaque[56];
__be64 next;
};
#define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
#define CDUT_SEG_ALIGNMET_IN_BYTES BIT(CDUT_SEG_ALIGNMET + 12)
#define CONN_CXT_SIZE(p_hwfn) \
ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
#define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context))
#define XRC_SRQ_CXT_SIZE (sizeof(struct rdma_xrc_srq_context))
#define TYPE0_TASK_CXT_SIZE(p_hwfn) \
ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
/* Alignment is inherent to the type1_task_context structure */
#define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
static bool src_proto(enum protocol_type type)
{
return type == PROTOCOLID_TCP_ULP ||
type == PROTOCOLID_FCOE ||
type == PROTOCOLID_IWARP;
}
static bool tm_cid_proto(enum protocol_type type)
{
return type == PROTOCOLID_TCP_ULP ||
type == PROTOCOLID_FCOE ||
type == PROTOCOLID_ROCE ||
type == PROTOCOLID_IWARP;
}
static bool tm_tid_proto(enum protocol_type type)
{
return type == PROTOCOLID_FCOE;
}
/* counts the iids for the CDU/CDUC ILT client configuration */
struct qed_cdu_iids {
u32 pf_cids;
u32 per_vf_cids;
};
static void qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr,
struct qed_cdu_iids *iids)
{
u32 type;
for (type = 0; type < MAX_CONN_TYPES; type++) {
iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
}
}
/* counts the iids for the Searcher block configuration */
struct qed_src_iids {
u32 pf_cids;
u32 per_vf_cids;
};
static void qed_cxt_src_iids(struct qed_cxt_mngr *p_mngr,
struct qed_src_iids *iids)
{
u32 i;
for (i = 0; i < MAX_CONN_TYPES; i++) {
if (!src_proto(i))
continue;
iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
}
/* Add L2 filtering filters in addition */
iids->pf_cids += p_mngr->arfs_count;
}
/* counts the iids for the Timers block configuration */
struct qed_tm_iids {
u32 pf_cids;
u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */
u32 pf_tids_total;
u32 per_vf_cids;
u32 per_vf_tids;
};
static void qed_cxt_tm_iids(struct qed_hwfn *p_hwfn,
Annotation
- Immediate include surface: `linux/types.h`, `linux/bitops.h`, `linux/dma-mapping.h`, `linux/errno.h`, `linux/kernel.h`, `linux/list.h`, `linux/log2.h`, `linux/pci.h`.
- Detected declarations: `struct src_ent`, `struct qed_cdu_iids`, `struct qed_src_iids`, `struct qed_tm_iids`, `function src_proto`, `function tm_cid_proto`, `function tm_tid_proto`, `function qed_cxt_cdu_iids`, `function qed_cxt_src_iids`, `function qed_cxt_tm_iids`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.