drivers/net/ethernet/qlogic/qed/qed_debug.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/qlogic/qed/qed_debug.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/qlogic/qed/qed_debug.c- Extension
.c- Size
- 245262 bytes
- Lines
- 8686
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches user memory; correctness depends on fault-safe copying and privilege boundary handling.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hlinux/vmalloc.hlinux/crc32.hqed.hqed_cxt.hqed_hsi.hqed_dbg_hsi.hqed_hw.hqed_mcp.hqed_reg_addr.h
Detected Declarations
struct framing_mode_defsstruct chip_defsstruct hw_type_defsstruct rbc_reset_defsstruct storm_defsstruct dbg_bus_constraint_op_defsstruct storm_mode_defsstruct grc_param_defsstruct rss_mem_defsstruct vfc_ram_defsstruct big_ram_defsstruct phy_defsstruct split_type_defsstruct reg_fifo_elementstruct reg_fifo_errstruct igu_fifo_elementstruct igu_fifo_wr_datastruct igu_fifo_cleanup_wr_datastruct protection_override_elementstruct igu_fifo_addr_dataenum mem_groupsenum hw_typesenum cm_ctx_typesenum dbg_bus_frame_modesenum dbg_bus_semi_frame_modesenum dbg_bus_filter_typesenum dbg_bus_pre_trigger_typesenum dbg_bus_post_trigger_typesenum dbg_bus_other_engine_modesenum igu_fifo_sourcesenum igu_fifo_addr_typesenum debug_print_featuresfunction cond5function cond7function cond6function cond9function cond10function cond4function cond0function cond14function cond1function cond11function cond12function cond3function cond13function cond8function cond2function qed_static_asserts
Annotated Snippet
struct framing_mode_defs {
u8 id;
u8 blocks_dword_mask;
u8 storms_dword_mask;
u8 semi_framing_mode_id;
u8 full_buf_thr;
};
/* Chip constant definitions */
struct chip_defs {
const char *name;
u8 dwords_per_cycle;
u8 num_framing_modes;
u32 num_ilt_pages;
struct framing_mode_defs *framing_modes;
};
/* HW type constant definitions */
struct hw_type_defs {
const char *name;
u32 delay_factor;
u32 dmae_thresh;
u32 log_thresh;
};
/* RBC reset definitions */
struct rbc_reset_defs {
u32 reset_reg_addr;
u32 reset_val[MAX_CHIP_IDS];
};
/* Storm constant definitions.
* Addresses are in bytes, sizes are in quad-regs.
*/
struct storm_defs {
char letter;
enum block_id sem_block_id;
enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS];
bool has_vfc;
u32 sem_fast_mem_addr;
u32 sem_frame_mode_addr;
u32 sem_slow_enable_addr;
u32 sem_slow_mode_addr;
u32 sem_slow_mode1_conf_addr;
u32 sem_sync_dbg_empty_addr;
u32 sem_gpre_vect_addr;
u32 cm_ctx_wr_addr;
u32 cm_ctx_rd_addr[NUM_CM_CTX_TYPES];
u32 cm_ctx_lid_sizes[MAX_CHIP_IDS][NUM_CM_CTX_TYPES];
};
/* Debug Bus Constraint operation constant definitions */
struct dbg_bus_constraint_op_defs {
u8 hw_op_val;
bool is_cyclic;
};
/* Storm Mode definitions */
struct storm_mode_defs {
const char *name;
bool is_fast_dbg;
u8 id_in_hw;
u32 src_disable_reg_addr;
u32 src_enable_val;
bool exists[MAX_CHIP_IDS];
};
struct grc_param_defs {
u32 default_val[MAX_CHIP_IDS];
u32 min;
u32 max;
bool is_preset;
bool is_persistent;
u32 exclude_all_preset_val;
u32 crash_preset_val[MAX_CHIP_IDS];
};
/* Address is in 128b units. Width is in bits. */
struct rss_mem_defs {
const char *mem_name;
const char *type_name;
u32 addr;
u32 entry_width;
u32 num_entries[MAX_CHIP_IDS];
};
struct vfc_ram_defs {
const char *mem_name;
const char *type_name;
u32 base_row;
Annotation
- Immediate include surface: `linux/module.h`, `linux/vmalloc.h`, `linux/crc32.h`, `qed.h`, `qed_cxt.h`, `qed_hsi.h`, `qed_dbg_hsi.h`, `qed_hw.h`.
- Detected declarations: `struct framing_mode_defs`, `struct chip_defs`, `struct hw_type_defs`, `struct rbc_reset_defs`, `struct storm_defs`, `struct dbg_bus_constraint_op_defs`, `struct storm_mode_defs`, `struct grc_param_defs`, `struct rss_mem_defs`, `struct vfc_ram_defs`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- This snippet crosses the user/kernel memory boundary; validate fault handling and access checks before translating the pattern.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.