drivers/net/ethernet/qlogic/qed/qed_int.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/qlogic/qed/qed_int.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/qlogic/qed/qed_int.c- Extension
.c- Size
- 69756 bytes
- Lines
- 2424
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/types.hasm/byteorder.hlinux/io.hlinux/bitops.hlinux/delay.hlinux/dma-mapping.hlinux/errno.hlinux/interrupt.hlinux/kernel.hlinux/pci.hlinux/slab.hlinux/string.hqed.hqed_hsi.hqed_hw.hqed_init_ops.hqed_int.hqed_mcp.hqed_reg_addr.hqed_sp.hqed_sriov.hqed_vf.h
Detected Declarations
struct qed_pi_infostruct qed_sb_sp_infostruct aeu_invert_reg_bitstruct aeu_invert_regstruct qed_sb_attn_infoenum qed_attention_typeenum aeu_invert_reg_special_typefunction qed_mcp_attn_cbfunction qed_pswhst_attn_cbfunction qed_grc_attn_cbfunction qed_pglueb_rbc_attn_handlerfunction qed_pglueb_rbc_attn_cbfunction qed_fw_assertionfunction qed_general_attention_35function qed_db_rec_flush_queuefunction addressfunction qed_db_rec_handlerfunction qed_dorq_attn_overflowfunction qed_dorq_attn_int_stsfunction qed_dorq_attn_cbfunction qed_dorq_attn_handlerfunction qed_int_aeu_translatefunction qed_int_is_parity_flagfunction qed_attn_update_idxfunction qed_int_assertionfunction qed_int_attn_printfunction qed_int_deassertion_aeu_bitfunction qed_int_deassertion_parityfunction qed_int_deassertionfunction qed_int_attentionsfunction qed_sb_ack_attnfunction qed_int_sp_dpcfunction qed_int_sb_attn_freefunction qed_int_sb_attn_setupfunction qed_int_sb_attn_initfunction qed_int_sb_attn_allocfunction qed_init_cau_sb_entryfunction qed_int_cau_conf_pifunction qed_int_cau_conf_sbfunction qed_int_sb_setupfunction qed_get_pf_igu_sb_idfunction qed_get_igu_sb_idfunction qed_int_sb_initfunction qed_int_sb_releasefunction qed_int_sp_sb_freefunction qed_int_sp_sb_allocfunction qed_int_register_cbfunction qed_int_unregister_cb
Annotated Snippet
struct qed_pi_info {
qed_int_comp_cb_t comp_cb;
void *cookie;
};
struct qed_sb_sp_info {
struct qed_sb_info sb_info;
/* per protocol index data */
struct qed_pi_info pi_info_arr[PIS_PER_SB];
};
enum qed_attention_type {
QED_ATTN_TYPE_ATTN,
QED_ATTN_TYPE_PARITY,
};
#define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
struct aeu_invert_reg_bit {
char bit_name[30];
#define ATTENTION_PARITY (1 << 0)
#define ATTENTION_LENGTH_MASK (0x00000ff0)
#define ATTENTION_LENGTH_SHIFT (4)
#define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \
ATTENTION_LENGTH_SHIFT)
#define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT)
#define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY)
#define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \
ATTENTION_PARITY)
/* Multiple bits start with this offset */
#define ATTENTION_OFFSET_MASK (0x000ff000)
#define ATTENTION_OFFSET_SHIFT (12)
#define ATTENTION_BB_MASK (0x00700000)
#define ATTENTION_BB_SHIFT (20)
#define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT)
#define ATTENTION_BB_DIFFERENT BIT(23)
#define ATTENTION_CLEAR_ENABLE BIT(28)
unsigned int flags;
/* Callback to call if attention will be triggered */
int (*cb)(struct qed_hwfn *p_hwfn);
enum block_id block_index;
};
struct aeu_invert_reg {
struct aeu_invert_reg_bit bits[32];
};
#define MAX_ATTN_GRPS (8)
#define NUM_ATTN_REGS (9)
/* Specific HW attention callbacks */
static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn)
{
u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
/* This might occur on certain instances; Log it once then mask it */
DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n",
tmp);
qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK,
0xffffffff);
return 0;
}
#define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1)
#define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1)
#define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0)
#define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf)
#define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1)
#define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1)
#define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5)
#define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff)
#define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6)
#define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf)
#define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14)
#define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff)
#define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18)
static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn)
{
u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
PSWHST_REG_INCORRECT_ACCESS_VALID);
Annotation
- Immediate include surface: `linux/types.h`, `asm/byteorder.h`, `linux/io.h`, `linux/bitops.h`, `linux/delay.h`, `linux/dma-mapping.h`, `linux/errno.h`, `linux/interrupt.h`.
- Detected declarations: `struct qed_pi_info`, `struct qed_sb_sp_info`, `struct aeu_invert_reg_bit`, `struct aeu_invert_reg`, `struct qed_sb_attn_info`, `enum qed_attention_type`, `enum aeu_invert_reg_special_type`, `function qed_mcp_attn_cb`, `function qed_pswhst_attn_cb`, `function qed_grc_attn_cb`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.