drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c- Extension
.c- Size
- 115971 bytes
- Lines
- 4242
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/if_vlan.hlinux/ipv6.hlinux/ethtool.hlinux/interrupt.hqlcnic.hqlcnic_sriov.h
Detected Declarations
function qlcnic_83xx_register_mapfunction qlcnic_83xx_get_fw_versionfunction __qlcnic_set_win_basefunction qlcnic_83xx_rd_reg_indirectfunction qlcnic_83xx_wrt_reg_indirectfunction qlcnic_83xx_enable_legacyfunction qlcnic_83xx_calculate_msix_vectorfunction qlcnic_83xx_setup_intrfunction qlcnic_83xx_clear_legacy_intr_maskfunction qlcnic_83xx_set_legacy_intr_maskfunction qlcnic_83xx_enable_legacy_msix_mbx_intrfunction qlcnic_83xx_disable_mbx_intrfunction qlcnic_83xx_get_mbx_datafunction qlcnic_83xx_clear_legacy_intrfunction qlcnic_83xx_notify_mbx_responsefunction qlcnic_83xx_poll_process_aenfunction qlcnic_83xx_intrfunction qlcnic_83xx_tmp_intrfunction qlcnic_83xx_free_mbx_intrfunction qlcnic_83xx_setup_mbx_intrfunction qlcnic_83xx_get_func_nofunction qlcnic_83xx_cam_lockfunction qlcnic_83xx_cam_unlockfunction qlcnic_83xx_read_crbfunction qlcnic_83xx_write_crbfunction qlcnic_83xx_get_port_infofunction qlcnic_83xx_set_mac_filter_countfunction qlcnic_83xx_enable_mbx_interruptfunction qlcnic_83xx_check_vffunction qlcnic_dump_mbxfunction qlcnic_83xx_poll_for_mbx_completionfunction qlcnic_83xx_issue_cmdfunction qlcnic_83xx_alloc_mbx_argsfunction qlcnic_83xx_idc_aen_workfunction qlcnic_83xx_handle_idc_comp_aenfunction __qlcnic_83xx_process_aenfunction qlcnic_83xx_process_aenfunction qlcnic_83xx_mbx_poll_workfunction qlcnic_83xx_enable_mbx_pollfunction qlcnic_83xx_disable_mbx_pollfunction qlcnic_83xx_add_ringsfunction qlcnic_83xx_del_rx_ctxfunction qlcnic_83xx_create_rx_ctxfunction qlcnic_83xx_del_tx_ctxfunction qlcnic_83xx_create_tx_ctxfunction qlcnic_83xx_diag_alloc_resfunction qlcnic_83xx_diag_free_resfunction qlcnic_83xx_get_beacon_state
Annotated Snippet
if (adapter->flags & QLCNIC_MSIX_ENABLED) {
num_msix = ahw->num_msix;
} else {
if (qlcnic_sriov_vf_check(adapter))
return -EINVAL;
num_msix = 1;
adapter->drv_sds_rings = QLCNIC_SINGLE_RING;
adapter->drv_tx_rings = QLCNIC_SINGLE_RING;
}
}
/* setup interrupt mapping table for fw */
ahw->intr_tbl =
vzalloc(array_size(num_msix,
sizeof(struct qlcnic_intrpt_config)));
if (!ahw->intr_tbl)
return -ENOMEM;
if (!(adapter->flags & QLCNIC_MSIX_ENABLED)) {
if (adapter->ahw->pci_func >= QLC_MAX_LEGACY_FUNC_SUPP) {
dev_err(&adapter->pdev->dev, "PCI function number 8 and higher are not supported with legacy interrupt, func 0x%x\n",
ahw->pci_func);
return -EOPNOTSUPP;
}
qlcnic_83xx_enable_legacy(adapter);
}
for (i = 0; i < num_msix; i++) {
if (adapter->flags & QLCNIC_MSIX_ENABLED)
ahw->intr_tbl[i].type = QLCNIC_INTRPT_MSIX;
else
ahw->intr_tbl[i].type = QLCNIC_INTRPT_INTX;
ahw->intr_tbl[i].id = i;
ahw->intr_tbl[i].src = 0;
}
return 0;
}
static inline void qlcnic_83xx_clear_legacy_intr_mask(struct qlcnic_adapter *adapter)
{
writel(0, adapter->tgt_mask_reg);
}
static inline void qlcnic_83xx_set_legacy_intr_mask(struct qlcnic_adapter *adapter)
{
if (adapter->tgt_mask_reg)
writel(1, adapter->tgt_mask_reg);
}
static inline void qlcnic_83xx_enable_legacy_msix_mbx_intr(struct qlcnic_adapter
*adapter)
{
u32 mask;
/* Mailbox in MSI-x mode and Legacy Interrupt share the same
* source register. We could be here before contexts are created
* and sds_ring->crb_intr_mask has not been initialized, calculate
* BAR offset for Interrupt Source Register
*/
mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
writel(0, adapter->ahw->pci_base0 + mask);
}
void qlcnic_83xx_disable_mbx_intr(struct qlcnic_adapter *adapter)
{
u32 mask;
mask = QLCRDX(adapter->ahw, QLCNIC_DEF_INT_MASK);
writel(1, adapter->ahw->pci_base0 + mask);
QLCWRX(adapter->ahw, QLCNIC_MBX_INTR_ENBL, 0);
}
static inline void qlcnic_83xx_get_mbx_data(struct qlcnic_adapter *adapter,
struct qlcnic_cmd_args *cmd)
{
int i;
if (cmd->op_type == QLC_83XX_MBX_POST_BC_OP)
return;
for (i = 0; i < cmd->rsp.num; i++)
cmd->rsp.arg[i] = readl(QLCNIC_MBX_FW(adapter->ahw, i));
}
irqreturn_t qlcnic_83xx_clear_legacy_intr(struct qlcnic_adapter *adapter)
{
u32 intr_val;
struct qlcnic_hardware_context *ahw = adapter->ahw;
Annotation
- Immediate include surface: `linux/if_vlan.h`, `linux/ipv6.h`, `linux/ethtool.h`, `linux/interrupt.h`, `qlcnic.h`, `qlcnic_sriov.h`.
- Detected declarations: `function qlcnic_83xx_register_map`, `function qlcnic_83xx_get_fw_version`, `function __qlcnic_set_win_base`, `function qlcnic_83xx_rd_reg_indirect`, `function qlcnic_83xx_wrt_reg_indirect`, `function qlcnic_83xx_enable_legacy`, `function qlcnic_83xx_calculate_msix_vector`, `function qlcnic_83xx_setup_intr`, `function qlcnic_83xx_clear_legacy_intr_mask`, `function qlcnic_83xx_set_legacy_intr_mask`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.