drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c- Extension
.c- Size
- 66089 bytes
- Lines
- 2601
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
qlcnic_sriov.hqlcnic.hqlcnic_hw.h
Detected Declarations
struct qlc_83xx_reset_hdrstruct qlc_83xx_entry_hdrstruct qlc_83xx_pollstruct qlc_83xx_rmwstruct qlc_83xx_entrystruct qlc_83xx_quad_entryfunction qlcnic_83xx_idc_check_driver_presence_regfunction qlcnic_83xx_idc_log_state_historyfunction qlcnic_83xx_idc_update_audit_regfunction qlcnic_83xx_idc_update_minor_versionfunction qlcnic_83xx_idc_update_major_versionfunction qlcnic_83xx_idc_update_drv_presence_regfunction qlcnic_83xx_idc_check_major_versionfunction qlcnic_83xx_idc_clear_registersfunction qlcnic_83xx_idc_update_drv_ack_regfunction qlcnic_83xx_idc_check_timeoutfunction qlcnic_83xx_idc_check_reset_ack_regfunction qlcnic_83xx_idc_tx_soft_resetfunction qlcnic_83xx_idc_detach_driverfunction qlcnic_83xx_idc_attach_driverfunction qlcnic_83xx_idc_enter_failed_statefunction qlcnic_83xx_idc_enter_init_statefunction qlcnic_83xx_idc_enter_need_quiescefunction qlcnic_83xx_idc_enter_need_reset_statefunction qlcnic_83xx_idc_enter_ready_statefunction qlcnic_83xx_idc_find_reset_owner_idfunction qlcnic_83xx_idc_restart_hwfunction qlcnic_83xx_idc_check_fan_failurefunction qlcnic_83xx_idc_reattach_driverfunction qlcnic_83xx_idc_update_idc_paramsfunction qlcnic_83xx_idc_ready_state_entryfunction qlcnic_83xx_idc_vnic_pf_entryfunction qlcnic_83xx_idc_unknown_statefunction qlcnic_83xx_idc_cold_state_handlerfunction qlcnic_83xx_idc_init_statefunction qlcnic_83xx_idc_ready_statefunction qlcnic_83xx_idc_need_reset_statefunction qlcnic_83xx_idc_need_quiesce_statefunction qlcnic_83xx_idc_failed_statefunction qlcnic_83xx_idc_quiesce_statefunction qlcnic_83xx_idc_check_state_validityfunction qlcnic_set_vxlan_portfunction qlcnic_set_vxlan_parsingfunction qlcnic_83xx_periodic_tasksfunction Communicationfunction qlcnic_83xx_setup_idc_parametersfunction qlcnic_83xx_idc_first_to_load_function_handlerfunction qlcnic_83xx_idc_init
Annotated Snippet
struct qlc_83xx_reset_hdr {
#if defined(__LITTLE_ENDIAN)
u16 version;
u16 signature;
u16 size;
u16 entries;
u16 hdr_size;
u16 checksum;
u16 init_offset;
u16 start_offset;
#elif defined(__BIG_ENDIAN)
u16 signature;
u16 version;
u16 entries;
u16 size;
u16 checksum;
u16 hdr_size;
u16 start_offset;
u16 init_offset;
#endif
} __packed;
/* Command entry header. */
struct qlc_83xx_entry_hdr {
#if defined(__LITTLE_ENDIAN)
u16 cmd;
u16 size;
u16 count;
u16 delay;
#elif defined(__BIG_ENDIAN)
u16 size;
u16 cmd;
u16 delay;
u16 count;
#endif
} __packed;
/* Generic poll command */
struct qlc_83xx_poll {
u32 mask;
u32 status;
} __packed;
/* Read modify write command */
struct qlc_83xx_rmw {
u32 mask;
u32 xor_value;
u32 or_value;
#if defined(__LITTLE_ENDIAN)
u8 shl;
u8 shr;
u8 index_a;
u8 rsvd;
#elif defined(__BIG_ENDIAN)
u8 rsvd;
u8 index_a;
u8 shr;
u8 shl;
#endif
} __packed;
/* Generic command with 2 DWORD */
struct qlc_83xx_entry {
u32 arg1;
u32 arg2;
} __packed;
/* Generic command with 4 DWORD */
struct qlc_83xx_quad_entry {
u32 dr_addr;
u32 dr_value;
u32 ar_addr;
u32 ar_value;
} __packed;
static const char *const qlc_83xx_idc_states[] = {
"Unknown",
"Cold",
"Init",
"Ready",
"Need Reset",
"Need Quiesce",
"Failed",
"Quiesce"
};
static int
qlcnic_83xx_idc_check_driver_presence_reg(struct qlcnic_adapter *adapter)
{
u32 val;
Annotation
- Immediate include surface: `qlcnic_sriov.h`, `qlcnic.h`, `qlcnic_hw.h`.
- Detected declarations: `struct qlc_83xx_reset_hdr`, `struct qlc_83xx_entry_hdr`, `struct qlc_83xx_poll`, `struct qlc_83xx_rmw`, `struct qlc_83xx_entry`, `struct qlc_83xx_quad_entry`, `function qlcnic_83xx_idc_check_driver_presence_reg`, `function qlcnic_83xx_idc_log_state_history`, `function qlcnic_83xx_idc_update_audit_reg`, `function qlcnic_83xx_idc_update_minor_version`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.