drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/qlogic/qlcnic/qlcnic.h- Extension
.h- Size
- 67223 bytes
- Lines
- 2418
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Allocates kernel memory; connect allocation flags and lifetime to context constraints.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
linux/module.hlinux/kernel.hlinux/types.hlinux/ioport.hlinux/pci.hlinux/netdevice.hlinux/etherdevice.hlinux/ip.hlinux/in.hlinux/tcp.hlinux/skbuff.hlinux/firmware.hlinux/ethtool.hlinux/mii.hlinux/timer.hlinux/irq.hlinux/vmalloc.hlinux/io.hasm/byteorder.hlinux/bitops.hlinux/if_vlan.hqlcnic_hdr.hqlcnic_hw.hqlcnic_83xx_hw.hqlcnic_dcb.h
Detected Declarations
struct cmd_desc_type0struct rcv_descstruct status_descstruct uni_table_descstruct uni_data_descstruct qlcnic_flt_headerstruct qlcnic_flt_entrystruct qlcnic_fdtstruct qlcnic_skb_fragstruct qlcnic_cmd_bufferstruct qlcnic_rx_bufferstruct qlcnic_nic_intr_coalescestruct qlcnic_83xx_dump_template_hdrstruct qlcnic_82xx_dump_template_hdrstruct qlcnic_fw_dumpstruct qlcnic_hardware_contextstruct qlcnic_adapter_statsstruct qlcnic_host_rds_ringstruct qlcnic_host_sds_ringstruct qlcnic_tx_queue_statsstruct qlcnic_host_tx_ringstruct qlcnic_recv_contextstruct qlcnic_hostrq_sds_ringstruct qlcnic_hostrq_rds_ringstruct qlcnic_hostrq_rx_ctxstruct qlcnic_cardrsp_rds_ringstruct qlcnic_cardrsp_sds_ringstruct qlcnic_cardrsp_rx_ctxstruct qlcnic_hostrq_cds_ringstruct qlcnic_hostrq_tx_ctxstruct qlcnic_cardrsp_cds_ringstruct qlcnic_cardrsp_tx_ctxstruct qlcnic_mac_vlan_liststruct qlcnic_fw_msgstruct qlcnic_nic_reqstruct qlcnic_mac_reqstruct qlcnic_vlan_reqstruct qlcnic_ipaddrstruct qlcnic_filterstruct qlcnic_filter_hashstruct qlcnic_mailboxstruct qlcnic_adapterstruct qlcnic_info_lestruct qlcnic_infostruct qlcnic_pci_info_lestruct qlcnic_pci_infostruct qlcnic_npar_infostruct qlcnic_eswitch
Annotated Snippet
struct cmd_desc_type0 {
u8 tcp_hdr_offset; /* For LSO only */
u8 ip_hdr_offset; /* For LSO only */
__le16 flags_opcode; /* 15:13 unused, 12:7 opcode, 6:0 flags */
__le32 nfrags__length; /* 31:8 total len, 7:0 frag count */
__le64 addr_buffer2;
__le16 encap_descr; /* 15:10 offset of outer L3 header,
* 9:6 number of 32bit words in outer L3 header,
* 5 offload outer L4 checksum,
* 4 offload outer L3 checksum,
* 3 Inner L4 type, TCP=0, UDP=1,
* 2 Inner L3 type, IPv4=0, IPv6=1,
* 1 Outer L3 type,IPv4=0, IPv6=1,
* 0 type of encapsulation, GRE=0, VXLAN=1
*/
__le16 mss;
u8 port_ctxid; /* 7:4 ctxid 3:0 port */
u8 hdr_length; /* LSO only : MAC+IP+TCP Hdr size */
u8 outer_hdr_length; /* Encapsulation only */
u8 rsvd1;
__le64 addr_buffer3;
__le64 addr_buffer1;
__le16 buffer_length[4];
__le64 addr_buffer4;
u8 eth_addr[ETH_ALEN];
__le16 vlan_TCI; /* In case of encapsulation,
* this is for outer VLAN
*/
} __attribute__ ((aligned(64)));
/* Note: sizeof(rcv_desc) should always be a mutliple of 2 */
struct rcv_desc {
__le16 reference_handle;
__le16 reserved;
__le32 buffer_length; /* allocated buffer length (usually 2K) */
__le64 addr_buffer;
} __packed;
struct status_desc {
__le64 status_desc_data[2];
} __attribute__ ((aligned(16)));
/* UNIFIED ROMIMAGE */
#define QLCNIC_UNI_FW_MIN_SIZE 0xc8000
#define QLCNIC_UNI_DIR_SECT_PRODUCT_TBL 0x0
#define QLCNIC_UNI_DIR_SECT_BOOTLD 0x6
#define QLCNIC_UNI_DIR_SECT_FW 0x7
/*Offsets */
#define QLCNIC_UNI_CHIP_REV_OFF 10
#define QLCNIC_UNI_FLAGS_OFF 11
#define QLCNIC_UNI_BIOS_VERSION_OFF 12
#define QLCNIC_UNI_BOOTLD_IDX_OFF 27
#define QLCNIC_UNI_FIRMWARE_IDX_OFF 29
struct uni_table_desc{
__le32 findex;
__le32 num_entries;
__le32 entry_size;
__le32 reserved[5];
};
struct uni_data_desc{
__le32 findex;
__le32 size;
__le32 reserved[5];
};
/* Flash Defines and Structures */
#define QLCNIC_FLT_LOCATION 0x3F1000
#define QLCNIC_FDT_LOCATION 0x3F0000
#define QLCNIC_B0_FW_IMAGE_REGION 0x74
#define QLCNIC_C0_FW_IMAGE_REGION 0x97
#define QLCNIC_BOOTLD_REGION 0X72
struct qlcnic_flt_header {
u16 version;
u16 len;
u16 checksum;
u16 reserved;
};
struct qlcnic_flt_entry {
u8 region;
Annotation
- Immediate include surface: `linux/module.h`, `linux/kernel.h`, `linux/types.h`, `linux/ioport.h`, `linux/pci.h`, `linux/netdevice.h`, `linux/etherdevice.h`, `linux/ip.h`.
- Detected declarations: `struct cmd_desc_type0`, `struct rcv_desc`, `struct status_desc`, `struct uni_table_desc`, `struct uni_data_desc`, `struct qlcnic_flt_header`, `struct qlcnic_flt_entry`, `struct qlcnic_fdt`, `struct qlcnic_skb_frag`, `struct qlcnic_cmd_buffer`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.