drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h
Extension
.h
Size
33501 bytes
Lines
948
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct qlcnic_legacy_intr_set {
	u32	int_vec_bit;
	u32	tgt_status_reg;
	u32	tgt_mask_reg;
	u32	pci_int_reg;
};

#define QLCNIC_MSIX_BASE	0x132110
#define QLCNIC_MAX_VLAN_FILTERS	64

#define FLASH_ROM_WINDOW	0x42110030
#define FLASH_ROM_DATA		0x42150000

#define QLCNIC_FW_DUMP_REG1	0x00130060
#define QLCNIC_FW_DUMP_REG2	0x001e0000
#define QLCNIC_FLASH_SEM2_LK	0x0013C010
#define QLCNIC_FLASH_SEM2_ULK	0x0013C014
#define QLCNIC_FLASH_LOCK_ID	0x001B2100

/* PCI function operational mode */
enum {
	QLCNIC_MGMT_FUNC	= 0,
	QLCNIC_PRIV_FUNC	= 1,
	QLCNIC_NON_PRIV_FUNC	= 2,
	QLCNIC_SRIOV_PF_FUNC	= 3,
	QLCNIC_SRIOV_VF_FUNC	= 4,
	QLCNIC_UNKNOWN_FUNC_MODE = 5
};

enum {
	QLCNIC_PORT_DEFAULTS	= 0,
	QLCNIC_ADD_VLAN	= 1,
	QLCNIC_DEL_VLAN	= 2
};

#define QLC_DEV_DRV_DEFAULT 0x11111111

#define LSB(x)	((uint8_t)(x))
#define MSB(x)	((uint8_t)((uint16_t)(x) >> 8))

#define LSW(x)  ((uint16_t)((uint32_t)(x)))
#define MSW(x)  ((uint16_t)((uint32_t)(x) >> 16))

#define LSD(x)  ((uint32_t)((uint64_t)(x)))
#define MSD(x)  ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))

#define QLCNIC_MS_CTRL			0x41000090
#define QLCNIC_MS_ADDR_LO		0x41000094
#define QLCNIC_MS_ADDR_HI		0x41000098
#define QLCNIC_MS_WRTDATA_LO		0x410000A0
#define QLCNIC_MS_WRTDATA_HI		0x410000A4
#define QLCNIC_MS_WRTDATA_ULO		0x410000B0
#define QLCNIC_MS_WRTDATA_UHI		0x410000B4
#define QLCNIC_MS_RDDATA_LO		0x410000A8
#define QLCNIC_MS_RDDATA_HI		0x410000AC
#define QLCNIC_MS_RDDATA_ULO		0x410000B8
#define QLCNIC_MS_RDDATA_UHI		0x410000BC

#define QLCNIC_TA_WRITE_ENABLE	(TA_CTL_ENABLE | TA_CTL_WRITE)
#define QLCNIC_TA_WRITE_START	(TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE)
#define QLCNIC_TA_START_ENABLE	(TA_CTL_START | TA_CTL_ENABLE)

#define	QLCNIC_LEGACY_INTR_CONFIG					\
{									\
	{								\
		.int_vec_bit	=	PCIX_INT_VECTOR_BIT_F0,		\
		.tgt_status_reg	=	ISR_INT_TARGET_STATUS,		\
		.tgt_mask_reg	=	ISR_INT_TARGET_MASK, },		\
									\
	{								\
		.int_vec_bit	=	PCIX_INT_VECTOR_BIT_F1,		\
		.tgt_status_reg	=	ISR_INT_TARGET_STATUS_F1,	\
		.tgt_mask_reg	=	ISR_INT_TARGET_MASK_F1, },	\
									\
	{								\
		.int_vec_bit	=	PCIX_INT_VECTOR_BIT_F2,		\
		.tgt_status_reg	=	ISR_INT_TARGET_STATUS_F2,	\
		.tgt_mask_reg	=	ISR_INT_TARGET_MASK_F2, },	\
									\
	{								\
		.int_vec_bit	=	PCIX_INT_VECTOR_BIT_F3,		\
		.tgt_status_reg	=	ISR_INT_TARGET_STATUS_F3,	\
		.tgt_mask_reg	=	ISR_INT_TARGET_MASK_F3, },	\
									\
	{								\
		.int_vec_bit	=	PCIX_INT_VECTOR_BIT_F4,		\
		.tgt_status_reg	=	ISR_INT_TARGET_STATUS_F4,	\
		.tgt_mask_reg	=	ISR_INT_TARGET_MASK_F4, },	\
									\
	{								\

Annotation

Implementation Notes