drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c

File Facts

System

Linux kernel

Corpus path

drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c

Extension

.c

Size

44739 bytes

Lines

1686

Domain

Driver Families

Bucket

drivers/net

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.
• Allocates kernel memory; connect allocation flags and lifetime to context constraints.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• linux/slab.h
• net/ip.h
• linux/bitops.h
• qlcnic.h
• qlcnic_hdr.h

Detected Declarations

• struct qlcnic_ms_reg_ctrl
• function readq
• function writeq
• function qlcnic_read_window_reg
• function qlcnic_write_window_reg
• function qlcnic_pcie_sem_lock
• function qlcnic_pcie_sem_unlock
• function qlcnic_ind_rd
• function qlcnic_ind_wr
• function qlcnic_send_cmd_descs
• function qlcnic_82xx_sre_macaddr_change
• function qlcnic_nic_del_mac
• function qlcnic_nic_add_mac
• function qlcnic_flush_mcast_mac
• function list_for_each_safe
• function __qlcnic_set_multi
• function qlcnic_set_multi
• function qlcnic_82xx_nic_set_promisc
• function qlcnic_82xx_free_mac_list
• function qlcnic_prune_lb_filters
• function hlist_for_each_entry_safe
• function hlist_for_each_entry_safe
• function qlcnic_delete_lb_filters
• function hlist_for_each_entry_safe
• function qlcnic_set_fw_loopback
• function qlcnic_82xx_set_lb_mode
• function qlcnic_82xx_clear_lb_mode
• function qlcnic_82xx_read_phys_port_id
• function qlcnic_82xx_set_rx_coalesce
• function qlcnic_82xx_config_intr_coalesce
• function qlcnic_82xx_config_hw_lro
• function qlcnic_config_bridged_mode
• function qlcnic_82xx_config_rss
• function qlcnic_82xx_config_ipaddr
• function qlcnic_82xx_linkevent_request
• function qlcnic_send_lro_cleanup
• function qlcnic_change_mtu
• function qlcnic_process_flags
• function qlcnic_fix_features
• function qlcnic_set_features
• function qlcnic_pci_get_crb_addr_2M
• function qlcnic_pci_set_crbwindow_2M
• function qlcnic_82xx_hw_write_wx_2M
• function qlcnic_82xx_hw_read_wx_2M
• function qlcnic_pci_mem_access_direct
• function qlcnic_pci_camqm_read_2M
• function qlcnic_pci_camqm_write_2M
• function qlcnic_set_ms_controls

Annotated Snippet

struct qlcnic_ms_reg_ctrl {
	u32 ocm_window;
	u32 control;
	u32 hi;
	u32 low;
	u32 rd[4];
	u32 wd[4];
	u64 off;
};

#ifndef readq
static inline u64 readq(void __iomem *addr)
{
	return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
}
#endif

#ifndef writeq
static inline void writeq(u64 val, void __iomem *addr)
{
	writel(((u32) (val)), (addr));
	writel(((u32) (val >> 32)), (addr + 4));
}
#endif

static struct crb_128M_2M_block_map
crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
    {{{0, 0,         0,         0} } },		/* 0: PCI */
    {{{1, 0x0100000, 0x0102000, 0x120000},	/* 1: PCIE */
	  {1, 0x0110000, 0x0120000, 0x130000},
	  {1, 0x0120000, 0x0122000, 0x124000},
	  {1, 0x0130000, 0x0132000, 0x126000},
	  {1, 0x0140000, 0x0142000, 0x128000},
	  {1, 0x0150000, 0x0152000, 0x12a000},
	  {1, 0x0160000, 0x0170000, 0x110000},
	  {1, 0x0170000, 0x0172000, 0x12e000},
	  {0, 0x0000000, 0x0000000, 0x000000},
	  {0, 0x0000000, 0x0000000, 0x000000},
	  {0, 0x0000000, 0x0000000, 0x000000},
	  {0, 0x0000000, 0x0000000, 0x000000},
	  {0, 0x0000000, 0x0000000, 0x000000},
	  {0, 0x0000000, 0x0000000, 0x000000},
	  {1, 0x01e0000, 0x01e0800, 0x122000},
	  {0, 0x0000000, 0x0000000, 0x000000} } },
	{{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
    {{{0, 0,         0,         0} } },	    /* 3: */
    {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
    {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE   */
    {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU   */
    {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM    */
    {{{1, 0x0800000, 0x0802000, 0x170000},  /* 8: SQM0  */
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {1, 0x08f0000, 0x08f2000, 0x172000} } },
    {{{1, 0x0900000, 0x0902000, 0x174000},	/* 9: SQM1*/
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {1, 0x09f0000, 0x09f2000, 0x176000} } },
    {{{0, 0x0a00000, 0x0a02000, 0x178000},	/* 10: SQM2*/
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},
      {0, 0x0000000, 0x0000000, 0x000000},

Annotation

• Immediate include surface: `linux/slab.h`, `net/ip.h`, `linux/bitops.h`, `qlcnic.h`, `qlcnic_hdr.h`.
• Detected declarations: `struct qlcnic_ms_reg_ctrl`, `function readq`, `function writeq`, `function qlcnic_read_window_reg`, `function qlcnic_write_window_reg`, `function qlcnic_pcie_sem_lock`, `function qlcnic_pcie_sem_unlock`, `function qlcnic_ind_rd`, `function qlcnic_ind_wr`, `function qlcnic_send_cmd_descs`.
• Atlas domain: Driver Families / drivers/net.
• Implementation status: source implementation candidate.
• Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.