drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c

File Facts

System

Linux kernel

Corpus path

drivers/net/ethernet/qlogic/qlcnic/qlcnic_minidump.c

Extension

.c

Size

35301 bytes

Lines

1455

Domain

Driver Families

Bucket

drivers/net

Inferred role

Driver Families: implementation source

Status

source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

• Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
• Uses kernel synchronization; read lock ordering, sleepability, and interrupt context assumptions before translating.
• Touches IRQ or DMA behavior; this matters for the representative real-device path.
• Allocates kernel memory; connect allocation flags and lifetime to context constraints.
• Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.

Dependency Surface

• net/ip.h
• qlcnic.h
• qlcnic_hdr.h
• qlcnic_83xx_hw.h
• qlcnic_hw.h

Detected Declarations

• struct qlcnic_pex_dma_descriptor
• struct qlcnic_common_entry_hdr
• struct __crb
• struct __ctrl
• struct __cache
• struct __ocm
• struct __mem
• struct __mux
• struct __queue
• struct __pollrd
• struct __mux2
• struct __pollrdmwr
• struct qlcnic_dump_entry
• struct qlcnic_dump_operations
• enum qlcnic_minidump_opcode
• function qlcnic_82xx_get_saved_state
• function qlcnic_82xx_set_saved_state
• function qlcnic_82xx_cache_tmpl_hdr_values
• function qlcnic_82xx_get_cap_size
• function qlcnic_82xx_set_sys_info
• function qlcnic_82xx_store_cap_mask
• function qlcnic_83xx_get_saved_state
• function qlcnic_83xx_set_saved_state
• function qlcnic_83xx_cache_tmpl_hdr_values
• function qlcnic_83xx_get_cap_size
• function qlcnic_83xx_set_sys_info
• function qlcnic_83xx_store_cap_mask
• function qlcnic_dump_crb
• function qlcnic_dump_ctrl
• function qlcnic_dump_mux
• function qlcnic_dump_que
• function qlcnic_dump_ocm
• function qlcnic_read_rom
• function qlcnic_dump_l1_cache
• function qlcnic_dump_l2_cache
• function qlcnic_read_memory_test_agent
• function qlcnic_start_pex_dma
• function qlcnic_read_memory_pexdma
• function qlcnic_read_memory
• function qlcnic_dump_nop
• function qlcnic_valid_dump_entry
• function qlcnic_read_pollrdmwr
• function qlcnic_read_pollrd
• function qlcnic_read_mux2
• function qlcnic_83xx_dump_rom
• function qlcnic_temp_checksum
• function qlcnic_fw_flash_get_minidump_temp
• function qlcnic_fw_flash_get_minidump_temp_size

Annotated Snippet

struct qlcnic_pex_dma_descriptor {
	u32	read_data_size;
	u32	dma_desc_cmd;
	u32	src_addr_low;
	u32	src_addr_high;
	u32	dma_bus_addr_low;
	u32	dma_bus_addr_high;
	u32	rsvd[6];
} __packed;

struct qlcnic_common_entry_hdr {
	u32     type;
	u32     offset;
	u32     cap_size;
#if defined(__LITTLE_ENDIAN)
	u8      mask;
	u8      rsvd[2];
	u8      flags;
#else
	u8      flags;
	u8      rsvd[2];
	u8      mask;
#endif
} __packed;

struct __crb {
	u32	addr;
#if defined(__LITTLE_ENDIAN)
	u8	stride;
	u8	rsvd1[3];
#else
	u8	rsvd1[3];
	u8	stride;
#endif
	u32	data_size;
	u32	no_ops;
	u32	rsvd2[4];
} __packed;

struct __ctrl {
	u32	addr;
#if defined(__LITTLE_ENDIAN)
	u8	stride;
	u8	index_a;
	u16	timeout;
#else
	u16	timeout;
	u8	index_a;
	u8	stride;
#endif
	u32	data_size;
	u32	no_ops;
#if defined(__LITTLE_ENDIAN)
	u8	opcode;
	u8	index_v;
	u8	shl_val;
	u8	shr_val;
#else
	u8	shr_val;
	u8	shl_val;
	u8	index_v;
	u8	opcode;
#endif
	u32	val1;
	u32	val2;
	u32	val3;
} __packed;

struct __cache {
	u32	addr;
#if defined(__LITTLE_ENDIAN)
	u16	stride;
	u16	init_tag_val;
#else
	u16	init_tag_val;
	u16	stride;
#endif
	u32	size;
	u32	no_ops;
	u32	ctrl_addr;
	u32	ctrl_val;
	u32	read_addr;
#if defined(__LITTLE_ENDIAN)
	u8	read_addr_stride;
	u8	read_addr_num;
	u8	rsvd1[2];
#else
	u8	rsvd1[2];
	u8	read_addr_num;
	u8	read_addr_stride;

Annotation

• Immediate include surface: `net/ip.h`, `qlcnic.h`, `qlcnic_hdr.h`, `qlcnic_83xx_hw.h`, `qlcnic_hw.h`.
• Detected declarations: `struct qlcnic_pex_dma_descriptor`, `struct qlcnic_common_entry_hdr`, `struct __crb`, `struct __ctrl`, `struct __cache`, `struct __ocm`, `struct __mem`, `struct __mux`, `struct __queue`, `struct __pollrd`.
• Atlas domain: Driver Families / drivers/net.
• Implementation status: source implementation candidate.
• Synchronization appears in or near this file; preserve lock ordering, sleepability, and interrupt-context constraints.
• IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.

Implementation Notes

• This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
• Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
• Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.