drivers/net/ethernet/qualcomm/ppe/ppe.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/qualcomm/ppe/ppe.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/qualcomm/ppe/ppe.c
Extension
.c
Size
6389 bytes
Lines
240
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
 */

/* PPE platform device probe, DTSI parser and PPE clock initializations. */

#include <linux/clk.h>
#include <linux/interconnect.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/reset.h>

#include "ppe.h"
#include "ppe_config.h"
#include "ppe_debugfs.h"

#define PPE_PORT_MAX		8
#define PPE_CLK_RATE		353000000

/* ICC clocks for enabling PPE device. The avg_bw and peak_bw with value 0
 * will be updated by the clock rate of PPE.
 */
static const struct icc_bulk_data ppe_icc_data[] = {
	{
		.name = "ppe",
		.avg_bw = 0,
		.peak_bw = 0,
	},
	{
		.name = "ppe_cfg",
		.avg_bw = 0,
		.peak_bw = 0,
	},
	{
		.name = "qos_gen",
		.avg_bw = 6000,
		.peak_bw = 6000,
	},
	{
		.name = "timeout_ref",
		.avg_bw = 6000,
		.peak_bw = 6000,
	},
	{
		.name = "nssnoc_memnoc",
		.avg_bw = 533333,
		.peak_bw = 533333,
	},
	{
		.name = "memnoc_nssnoc",
		.avg_bw = 533333,
		.peak_bw = 533333,
	},
	{
		.name = "memnoc_nssnoc_1",
		.avg_bw = 533333,
		.peak_bw = 533333,
	},
};

static const struct regmap_range ppe_readable_ranges[] = {
	regmap_reg_range(0x0, 0x1ff),		/* Global */
	regmap_reg_range(0x400, 0x5ff),		/* LPI CSR */
	regmap_reg_range(0x1000, 0x11ff),	/* GMAC0 */
	regmap_reg_range(0x1200, 0x13ff),	/* GMAC1 */
	regmap_reg_range(0x1400, 0x15ff),	/* GMAC2 */
	regmap_reg_range(0x1600, 0x17ff),	/* GMAC3 */
	regmap_reg_range(0x1800, 0x19ff),	/* GMAC4 */
	regmap_reg_range(0x1a00, 0x1bff),	/* GMAC5 */
	regmap_reg_range(0xb000, 0xefff),	/* PRX CSR */
	regmap_reg_range(0xf000, 0x1efff),	/* IPE */
	regmap_reg_range(0x20000, 0x5ffff),	/* PTX CSR */
	regmap_reg_range(0x60000, 0x9ffff),	/* IPE L2 CSR */
	regmap_reg_range(0xb0000, 0xeffff),	/* IPO CSR */
	regmap_reg_range(0x100000, 0x17ffff),	/* IPE PC */
	regmap_reg_range(0x180000, 0x1bffff),	/* PRE IPO CSR */
	regmap_reg_range(0x1d0000, 0x1dffff),	/* Tunnel parser */
	regmap_reg_range(0x1e0000, 0x1effff),	/* Ingress parse */
	regmap_reg_range(0x200000, 0x2fffff),	/* IPE L3 */
	regmap_reg_range(0x300000, 0x3fffff),	/* IPE tunnel */
	regmap_reg_range(0x400000, 0x4fffff),	/* Scheduler */
	regmap_reg_range(0x500000, 0x503fff),	/* XGMAC0 */
	regmap_reg_range(0x504000, 0x507fff),	/* XGMAC1 */
	regmap_reg_range(0x508000, 0x50bfff),	/* XGMAC2 */
	regmap_reg_range(0x50c000, 0x50ffff),	/* XGMAC3 */
	regmap_reg_range(0x510000, 0x513fff),	/* XGMAC4 */

Annotation

Implementation Notes