drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
Extension
.h
Size
24755 bytes
Lines
592
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

#ifndef __PPE_REGS_H__
#define __PPE_REGS_H__

#include <linux/bitfield.h>

/* PPE scheduler configurations for buffer manager block. */
#define PPE_BM_SCH_CTRL_ADDR			0xb000
#define PPE_BM_SCH_CTRL_INC			4
#define PPE_BM_SCH_CTRL_SCH_DEPTH		GENMASK(7, 0)
#define PPE_BM_SCH_CTRL_SCH_OFFSET		GENMASK(14, 8)
#define PPE_BM_SCH_CTRL_SCH_EN			BIT(31)

/* PPE drop counters. */
#define PPE_DROP_CNT_TBL_ADDR			0xb024
#define PPE_DROP_CNT_TBL_ENTRIES		8
#define PPE_DROP_CNT_TBL_INC			4

/* BM port drop counters. */
#define PPE_DROP_STAT_TBL_ADDR			0xe000
#define PPE_DROP_STAT_TBL_ENTRIES		30
#define PPE_DROP_STAT_TBL_INC			0x10

/* Egress VLAN counters. */
#define PPE_EG_VSI_COUNTER_TBL_ADDR		0x41000
#define PPE_EG_VSI_COUNTER_TBL_ENTRIES		64
#define PPE_EG_VSI_COUNTER_TBL_INC		0x10

/* Port TX counters. */
#define PPE_PORT_TX_COUNTER_TBL_ADDR		0x45000
#define PPE_PORT_TX_COUNTER_TBL_ENTRIES		8
#define PPE_PORT_TX_COUNTER_TBL_INC		0x10

/* Virtual port TX counters. */
#define PPE_VPORT_TX_COUNTER_TBL_ADDR		0x47000
#define PPE_VPORT_TX_COUNTER_TBL_ENTRIES	256
#define PPE_VPORT_TX_COUNTER_TBL_INC		0x10

/* Queue counters. */
#define PPE_QUEUE_TX_COUNTER_TBL_ADDR		0x4a000
#define PPE_QUEUE_TX_COUNTER_TBL_ENTRIES	300
#define PPE_QUEUE_TX_COUNTER_TBL_INC		0x10

/* RSS settings are to calculate the random RSS hash value generated during
 * packet receive to ARM cores. This hash is then used to generate the queue
 * offset used to determine the queue used to transmit the packet to ARM cores.
 */
#define PPE_RSS_HASH_MASK_ADDR			0xb4318
#define PPE_RSS_HASH_MASK_HASH_MASK		GENMASK(20, 0)
#define PPE_RSS_HASH_MASK_FRAGMENT		BIT(28)

#define PPE_RSS_HASH_SEED_ADDR			0xb431c
#define PPE_RSS_HASH_SEED_VAL			GENMASK(31, 0)

#define PPE_RSS_HASH_MIX_ADDR			0xb4320
#define PPE_RSS_HASH_MIX_ENTRIES		11
#define PPE_RSS_HASH_MIX_INC			4
#define PPE_RSS_HASH_MIX_VAL			GENMASK(4, 0)

#define PPE_RSS_HASH_FIN_ADDR			0xb4350
#define PPE_RSS_HASH_FIN_ENTRIES		5
#define PPE_RSS_HASH_FIN_INC			4
#define PPE_RSS_HASH_FIN_INNER			GENMASK(4, 0)
#define PPE_RSS_HASH_FIN_OUTER			GENMASK(9, 5)

#define PPE_RSS_HASH_MASK_IPV4_ADDR		0xb4380
#define PPE_RSS_HASH_MASK_IPV4_HASH_MASK	GENMASK(20, 0)
#define PPE_RSS_HASH_MASK_IPV4_FRAGMENT		BIT(28)

#define PPE_RSS_HASH_SEED_IPV4_ADDR		0xb4384
#define PPE_RSS_HASH_SEED_IPV4_VAL		GENMASK(31, 0)

#define PPE_RSS_HASH_MIX_IPV4_ADDR		0xb4390
#define PPE_RSS_HASH_MIX_IPV4_ENTRIES		5
#define PPE_RSS_HASH_MIX_IPV4_INC		4
#define PPE_RSS_HASH_MIX_IPV4_VAL		GENMASK(4, 0)

#define PPE_RSS_HASH_FIN_IPV4_ADDR		0xb43b0
#define PPE_RSS_HASH_FIN_IPV4_ENTRIES		5
#define PPE_RSS_HASH_FIN_IPV4_INC		4
#define PPE_RSS_HASH_FIN_IPV4_INNER		GENMASK(4, 0)
#define PPE_RSS_HASH_FIN_IPV4_OUTER		GENMASK(9, 5)

#define PPE_BM_SCH_CFG_TBL_ADDR			0xc000
#define PPE_BM_SCH_CFG_TBL_ENTRIES		128
#define PPE_BM_SCH_CFG_TBL_INC			0x10
#define PPE_BM_SCH_CFG_TBL_PORT_NUM		GENMASK(3, 0)
#define PPE_BM_SCH_CFG_TBL_DIR			BIT(4)
#define PPE_BM_SCH_CFG_TBL_VALID		BIT(5)
#define PPE_BM_SCH_CFG_TBL_SECOND_PORT_VALID	BIT(6)
#define PPE_BM_SCH_CFG_TBL_SECOND_PORT		GENMASK(11, 8)

Annotation

Implementation Notes