drivers/net/ethernet/realtek/rtase/rtase.h
Source file repositories/reference/linux-study-clean/drivers/net/ethernet/realtek/rtase/rtase.h
File Facts
- System
- Linux kernel
- Corpus path
drivers/net/ethernet/realtek/rtase/rtase.h- Extension
.h- Size
- 9902 bytes
- Lines
- 367
- Domain
- Driver Families
- Bucket
- drivers/net
- Inferred role
- Driver Families: implementation source
- Status
- source implementation candidate
Why This File Exists
Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.
- Touches IRQ or DMA behavior; this matters for the representative real-device path.
- Defines or uses C structs; map object ownership, embedded links, reference counts, and lock ownership.
Dependency Surface
- No C-style include directives detected by the generator.
Detected Declarations
struct rtase_tx_descstruct rtase_int_vectorstruct rtase_ringstruct rtase_txqosstruct rtase_statsstruct rtase_privateenum rtase_registersenum rtase_desc_status_bitenum rtase_sw_flag_content
Annotated Snippet
struct rtase_tx_desc {
__le32 opts1;
__le32 opts2;
__le64 addr;
__le32 opts3;
__le32 reserved1;
__le32 reserved2;
__le32 reserved3;
} __packed;
/*------ offset 0 of tx descriptor ------*/
#define RTASE_TX_FIRST_FRAG BIT(29) /* Tx First segment of a packet */
#define RTASE_TX_LAST_FRAG BIT(28) /* Tx Final segment of a packet */
#define RTASE_GIANT_SEND_V4 BIT(26) /* TCP Giant Send Offload V4 (GSOv4) */
#define RTASE_GIANT_SEND_V6 BIT(25) /* TCP Giant Send Offload V6 (GSOv6) */
#define RTASE_TX_VLAN_TAG BIT(17) /* Add VLAN tag */
/*------ offset 4 of tx descriptor ------*/
#define RTASE_TX_UDPCS_C BIT(31) /* Calculate UDP/IP checksum */
#define RTASE_TX_TCPCS_C BIT(30) /* Calculate TCP/IP checksum */
#define RTASE_TX_IPCS_C BIT(29) /* Calculate IP checksum */
#define RTASE_TX_IPV6F_C BIT(28) /* Indicate it is an IPv6 packet */
union rtase_rx_desc {
struct {
__le64 header_buf_addr;
__le32 reserved1;
__le32 opts_header_len;
__le64 addr;
__le32 reserved2;
__le32 opts1;
} __packed desc_cmd;
struct {
__le32 reserved1;
__le32 reserved2;
__le32 rss;
__le32 opts4;
__le32 reserved3;
__le32 opts3;
__le32 opts2;
__le32 opts1;
} __packed desc_status;
} __packed;
/*------ offset 28 of rx descriptor ------*/
#define RTASE_RX_FIRST_FRAG BIT(25) /* Rx First segment of a packet */
#define RTASE_RX_LAST_FRAG BIT(24) /* Rx Final segment of a packet */
#define RTASE_RX_RES BIT(20)
#define RTASE_RX_RUNT BIT(19)
#define RTASE_RX_RWT BIT(18)
#define RTASE_RX_CRC BIT(17)
#define RTASE_RX_V6F BIT(31)
#define RTASE_RX_V4F BIT(30)
#define RTASE_RX_UDPT BIT(29)
#define RTASE_RX_TCPT BIT(28)
#define RTASE_RX_IPF BIT(26) /* IP checksum failed */
#define RTASE_RX_UDPF BIT(25) /* UDP/IP checksum failed */
#define RTASE_RX_TCPF BIT(24) /* TCP/IP checksum failed */
#define RTASE_RX_VLAN_TAG BIT(16) /* VLAN tag available */
#define RTASE_NUM_DESC 1024
#define RTASE_TX_BUDGET_DEFAULT 256
#define RTASE_TX_RING_DESC_SIZE (RTASE_NUM_DESC * sizeof(struct rtase_tx_desc))
#define RTASE_RX_RING_DESC_SIZE (RTASE_NUM_DESC * sizeof(union rtase_rx_desc))
#define RTASE_TX_STOP_THRS (MAX_SKB_FRAGS + 1)
#define RTASE_TX_START_THRS (2 * RTASE_TX_STOP_THRS)
#define RTASE_VLAN_TAG_MASK GENMASK(15, 0)
#define RTASE_RX_PKT_SIZE_MASK GENMASK(13, 0)
/* txqos hardware definitions */
#define RTASE_1T_CLOCK 64
#define RTASE_1T_POWER 10000000
#define RTASE_IDLESLOPE_INT_SHIFT 25
#define RTASE_IDLESLOPE_INT_MASK GENMASK(31, 25)
#define RTASE_IVEC_NAME_SIZE (IFNAMSIZ + 10)
struct rtase_int_vector {
struct rtase_private *tp;
unsigned int irq;
char name[RTASE_IVEC_NAME_SIZE];
u16 index;
u16 imr_addr;
u16 isr_addr;
u32 imr;
struct list_head ring_list;
struct napi_struct napi;
int (*poll)(struct napi_struct *napi, int budget);
};
Annotation
- Detected declarations: `struct rtase_tx_desc`, `struct rtase_int_vector`, `struct rtase_ring`, `struct rtase_txqos`, `struct rtase_stats`, `struct rtase_private`, `enum rtase_registers`, `enum rtase_desc_status_bit`, `enum rtase_sw_flag_content`.
- Atlas domain: Driver Families / drivers/net.
- Implementation status: source implementation candidate.
- IRQ or DMA behavior appears here, which is relevant to the selected PCIe/NVMe device path.
Implementation Notes
- This generated page is the file-by-file coverage layer; curated subsystem chapters should link here when they synthesize a multi-file control flow.
- Core OS pages should be promoted from atlas-only to deep-reviewed when they explain data structures, invariants, locking, lifecycle, and C implementation snippets.
- Driver-family pages are intentionally pattern-oriented unless they are part of the selected PCIe/NVMe representative device path.