drivers/net/ethernet/renesas/ravb.h

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/renesas/ravb.h

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/renesas/ravb.h
Extension
.h
Size
26539 bytes
Lines
1167
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

struct ravb_desc {
	__le16 ds;	/* Descriptor size */
	u8 cc;		/* Content control MSBs (reserved) */
	u8 die_dt;	/* Descriptor interrupt enable and type */
	__le32 dptr;	/* Descriptor pointer */
};

#define DPTR_ALIGN	4	/* Required descriptor pointer alignment */

enum DIE_DT {
	/* Frame data */
	DT_FMID		= 0x40,
	DT_FSTART	= 0x50,
	DT_FEND		= 0x60,
	DT_FSINGLE	= 0x70,
	/* Chain control */
	DT_LINK		= 0x80,
	DT_LINKFIX	= 0x90,
	DT_EOS		= 0xa0,
	/* HW/SW arbitration */
	DT_FEMPTY	= 0xc0,
	DT_FEMPTY_IS	= 0xd0,
	DT_FEMPTY_IC	= 0xe0,
	DT_FEMPTY_ND	= 0xf0,
	DT_LEMPTY	= 0x20,
	DT_EEMPTY	= 0x30,
};

struct ravb_rx_desc {
	__le16 ds_cc;	/* Descriptor size and content control LSBs */
	u8 msc;		/* MAC status code */
	u8 die_dt;	/* Descriptor interrupt enable and type */
	__le32 dptr;	/* Descpriptor pointer */
};

struct ravb_ex_rx_desc {
	__le16 ds_cc;	/* Descriptor size and content control lower bits */
	u8 msc;		/* MAC status code */
	u8 die_dt;	/* Descriptor interrupt enable and type */
	__le32 dptr;	/* Descpriptor pointer */
	__le32 ts_n;	/* Timestampe nsec */
	__le32 ts_sl;	/* Timestamp low */
	__le16 ts_sh;	/* Timestamp high */
	__le16 res;	/* Reserved bits */
};

enum RX_DS_CC_BIT {
	RX_DS		= 0x0fff, /* Data size */
	RX_TR		= 0x1000, /* Truncation indication */
	RX_EI		= 0x2000, /* Error indication */
	RX_PS		= 0xc000, /* Padding selection */
};

/* E-MAC status code */
enum MSC_BIT {
	MSC_CRC		= 0x01, /* Frame CRC error */
	MSC_RFE		= 0x02, /* Frame reception error (flagged by PHY) */
	MSC_RTSF	= 0x04, /* Frame length error (frame too short) */
	MSC_RTLF	= 0x08, /* Frame length error (frame too long) */
	MSC_FRE		= 0x10, /* Fraction error (not a multiple of 8 bits) */
	MSC_CRL		= 0x20, /* Carrier lost */
	MSC_CEEF	= 0x40, /* Carrier extension error */
	MSC_MC		= 0x80, /* Multicast frame reception */
};

struct ravb_tx_desc {
	__le16 ds_tagl;	/* Descriptor size and frame tag LSBs */
	u8 tagh_tsr;	/* Frame tag MSBs and timestamp storage request bit */
	u8 die_dt;	/* Descriptor interrupt enable and type */
	__le32 dptr;	/* Descpriptor pointer */
};

enum TX_DS_TAGL_BIT {
	TX_DS		= 0x0fff, /* Data size */
	TX_TAGL		= 0xf000, /* Frame tag LSBs */
};

enum TX_TAGH_TSR_BIT {
	TX_TAGH		= 0x3f, /* Frame tag MSBs */
	TX_TSR		= 0x40, /* Timestamp storage request */
};
enum RAVB_QUEUE {
	RAVB_BE = 0,	/* Best Effort Queue */
	RAVB_NC,	/* Network Control Queue */
};

enum CXR31_BIT {
	CXR31_SEL_LINK0	= 0x00000001,
	CXR31_SEL_LINK1	= 0x00000008,
};

Annotation

Implementation Notes