drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/samsung/sxgbe/sxgbe_dma.c
Extension
.c
Size
10280 bytes
Lines
366
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

if (int_status & SXGBE_DMA_INT_STATUS_TI) {
			ret_val |= handle_tx;
			x->tx_normal_irq_n++;
			clear_val |= SXGBE_DMA_INT_STATUS_TI;
		}

		if (int_status & SXGBE_DMA_INT_STATUS_TBU) {
			x->tx_underflow_irq++;
			ret_val |= tx_bump_tc;
			clear_val |= SXGBE_DMA_INT_STATUS_TBU;
		}
	} else if (unlikely(int_status & SXGBE_DMA_INT_STATUS_AIS)) {
		/* TX Abnormal Interrupt Summary */
		if (int_status & SXGBE_DMA_INT_STATUS_TPS) {
			ret_val |= tx_hard_error;
			clear_val |= SXGBE_DMA_INT_STATUS_TPS;
			x->tx_process_stopped_irq++;
		}

		if (int_status & SXGBE_DMA_INT_STATUS_FBE) {
			ret_val |= tx_hard_error;
			x->fatal_bus_error_irq++;

			/* Assumption: FBE bit is the combination of
			 * all the bus access erros and cleared when
			 * the respective error bits cleared
			 */

			/* check for actual cause */
			if (int_status & SXGBE_DMA_INT_STATUS_TEB0) {
				x->tx_read_transfer_err++;
				clear_val |= SXGBE_DMA_INT_STATUS_TEB0;
			} else {
				x->tx_write_transfer_err++;
			}

			if (int_status & SXGBE_DMA_INT_STATUS_TEB1) {
				x->tx_desc_access_err++;
				clear_val |= SXGBE_DMA_INT_STATUS_TEB1;
			} else {
				x->tx_buffer_access_err++;
			}

			if (int_status & SXGBE_DMA_INT_STATUS_TEB2) {
				x->tx_data_transfer_err++;
				clear_val |= SXGBE_DMA_INT_STATUS_TEB2;
			}
		}

		/* context descriptor error */
		if (int_status & SXGBE_DMA_INT_STATUS_CTXTERR) {
			x->tx_ctxt_desc_err++;
			clear_val |= SXGBE_DMA_INT_STATUS_CTXTERR;
		}
	}

	/* clear the served bits */
	writel(clear_val, ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no));

	return ret_val;
}

static int sxgbe_rx_dma_int_status(void __iomem *ioaddr, int channel_no,
				   struct sxgbe_extra_stats *x)
{
	u32 int_status = readl(ioaddr + SXGBE_DMA_CHA_STATUS_REG(channel_no));
	u32 clear_val = 0;
	u32 ret_val = 0;

	/* RX Normal Interrupt Summary */
	if (likely(int_status & SXGBE_DMA_INT_STATUS_NIS)) {
		x->normal_irq_n++;
		if (int_status & SXGBE_DMA_INT_STATUS_RI) {
			ret_val |= handle_rx;
			x->rx_normal_irq_n++;
			clear_val |= SXGBE_DMA_INT_STATUS_RI;
		}
	} else if (unlikely(int_status & SXGBE_DMA_INT_STATUS_AIS)) {
		/* RX Abnormal Interrupt Summary */
		if (int_status & SXGBE_DMA_INT_STATUS_RBU) {
			ret_val |= rx_bump_tc;
			clear_val |= SXGBE_DMA_INT_STATUS_RBU;
			x->rx_underflow_irq++;
		}

		if (int_status & SXGBE_DMA_INT_STATUS_RPS) {
			ret_val |= rx_hard_error;
			clear_val |= SXGBE_DMA_INT_STATUS_RPS;
			x->rx_process_stopped_irq++;
		}

Annotation

Implementation Notes