drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

Source file repositories/reference/linux-study-clean/drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c

File Facts

System
Linux kernel
Corpus path
drivers/net/ethernet/samsung/sxgbe/sxgbe_mtl.c
Extension
.c
Size
6790 bytes
Lines
252
Domain
Driver Families
Bucket
drivers/net
Inferred role
Driver Families: implementation source
Status
source implementation candidate

Why This File Exists

Repeatable hardware-adapter layer. Deep compatibility for every driver is out of scope; this atlas records patterns, probe lifecycles, bus glue, IRQ/DMA usage, and links back to core abstractions.

Dependency Surface

Detected Declarations

Annotated Snippet

// SPDX-License-Identifier: GPL-2.0-only
/* 10G controller driver for Samsung SoCs
 *
 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
 *		http://www.samsung.com
 *
 * Author: Siva Reddy Kallam <siva.kallam@samsung.com>
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/io.h>
#include <linux/errno.h>
#include <linux/export.h>
#include <linux/jiffies.h>

#include "sxgbe_mtl.h"
#include "sxgbe_reg.h"

static void sxgbe_mtl_init(void __iomem *ioaddr, unsigned int etsalg,
			   unsigned int raa)
{
	u32 reg_val;

	reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG);
	reg_val &= ETS_RST;

	/* ETS Algorithm */
	switch (etsalg & SXGBE_MTL_OPMODE_ESTMASK) {
	case ETS_WRR:
		reg_val &= ETS_WRR;
		break;
	case ETS_WFQ:
		reg_val |= ETS_WFQ;
		break;
	case ETS_DWRR:
		reg_val |= ETS_DWRR;
		break;
	}
	writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);

	switch (raa & SXGBE_MTL_OPMODE_RAAMASK) {
	case RAA_SP:
		reg_val &= RAA_SP;
		break;
	case RAA_WSP:
		reg_val |= RAA_WSP;
		break;
	}
	writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG);
}

/* For Dynamic DMA channel mapping for Rx queue */
static void sxgbe_mtl_dma_dm_rxqueue(void __iomem *ioaddr)
{
	writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP0_REG);
	writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP1_REG);
	writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP2_REG);
}

static void sxgbe_mtl_set_txfifosize(void __iomem *ioaddr, int queue_num,
				     int queue_fifo)
{
	u32 fifo_bits, reg_val;

	/* 0 means 256 bytes */
	fifo_bits = (queue_fifo / SXGBE_MTL_TX_FIFO_DIV) - 1;
	reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
	reg_val |= (fifo_bits << SXGBE_MTL_FIFO_LSHIFT);
	writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
}

static void sxgbe_mtl_set_rxfifosize(void __iomem *ioaddr, int queue_num,
				     int queue_fifo)
{
	u32 fifo_bits, reg_val;

	/* 0 means 256 bytes */
	fifo_bits = (queue_fifo / SXGBE_MTL_RX_FIFO_DIV)-1;
	reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
	reg_val |= (fifo_bits << SXGBE_MTL_FIFO_LSHIFT);
	writel(reg_val, ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num));
}

static void sxgbe_mtl_enable_txqueue(void __iomem *ioaddr, int queue_num)
{
	u32 reg_val;

	reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num));
	reg_val |= SXGBE_MTL_ENABLE_QUEUE;

Annotation

Implementation Notes